Memory Device Current Compensation Circuit for Leakage Management
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Solution Overview
Problem
Memory devices using resistance, such as PRAM and ReRAM, face challenges in maintaining a sufficient sensing margin due to leakage currents from non-selected memory cells, which affect the accuracy of readout operations.
Innovation Solution
The implementation of a current compensation circuit and adjusting the enabling time of sense amplifiers to compensate for leakage currents, ensuring accurate readout operations by maintaining a sufficient sensing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a memory device uses resistance to store data, then write operations can be performed using resistance changes, but leakage currents from non-selected memory cells reduce sensing margin and readout accuracy
Solution Approach 1:
The patent divides the bit lines into multiple segments by introducing local bit lines and global bit lines. Local bit lines are connected to specific memory cell regions, while global bit lines connect multiple local bit lines. This segmentation allows the sensing operation to be isolated to specific regions, preventing leakage currents from non-selected memory cells from affecting the sensing margin of selected memory cells.
Solution Approach 2:
The patent introduces intermediate circuits including local sense amplifiers connected to local bit lines and a global sense amplifier connected to global bit lines. These intermediate sense amplifiers act as mediators that amplify signals from local bit lines before they reach the global sense amplifier, thereby maintaining sensing margin by preventing the degradation of signal strength caused by leakage currents in non-selected regions.
2Speed
If sense amplifiers are enabled early to detect voltage changes, then readout speed improves, but leakage currents from non-selected bit lines reduce measurement accuracy
Solution Approach 1:
The patent applies preliminary action by pre-charging local bit lines to a predetermined voltage level before the sensing operation begins. This pre-charging ensures that when the sense amplifier is enabled, the voltage difference caused by the memory cell state can be detected immediately without waiting for voltage buildup, thus improving readout speed while maintaining accuracy. The local sense amplifier is enabled at a precisely controlled timing to detect voltage changes before leakage currents from non-selected bit lines can significantly affect the measurement.
3Measurement precision
If compensation current is increased to offset leakage currents, then sensing margin is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by providing compensation current only to the local bit lines that are actively being sensed, rather than to all bit lines in the memory array. The local sense amplifier generates compensation current locally at the region where sensing is occurring, which offsets leakage currents only in that specific region. This localized approach maintains sensing margin in the active region while minimizing power consumption by avoiding unnecessary compensation current in inactive regions.
Data Source
AI summary
A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.