Low Power Delay Buffer Between Equalizer and Slicer
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Solution Overview
Problem
Conventional double data rate data buffer circuit designs and registered clock driver circuit designs face challenges in reducing power consumption, especially at synchronization signal frequencies above 2.2 GHz to 3.2 GHz, where significant power is consumed to delay data signals due to clock trees, and equalizer frequency performance is affected by decision feedback equalizer circuitry.
Innovation Solution
A low power delay buffer is implemented between an equalizer and a high sensitivity slicer, using a continuous-time linear equalizer circuit with a source follower delay buffer and a strongARM latch, which provides low power consumption, high signal bandwidth, and programmable delay to match data and clock signal timing, isolating the equalizer from the decision feedback equalizer circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional fold buffer or differential-to-single-end latch designs are used to delay data signals, then timing alignment between data and clock signals is achieved, but power consumption increases significantly
Solution Approach 1:
The patent replaces conventional mechanical/latch-based delay circuits with a continuous-time linear equalizer (CTLE) approach that uses transconductance amplification. This substitution eliminates the need for discrete latch cycles, achieving smooth continuous delay without the power consumption associated with conventional buffering mechanisms.
Solution Approach 2:
The invention changes the operating parameters by using transconductance-based continuous-time processing instead of voltage-based discrete latching. This parameter change enables delay functionality to be achieved through continuous signal processing rather than discrete state transitions, significantly reducing power consumption while maintaining timing alignment.
2Reliability
If decision feedback equalizer circuitry is added to improve equalizer frequency performance, then signal quality is enhanced, but power consumption and circuit complexity increase
Solution Approach 1:
The patent extracts and removes the decision feedback equalizer circuitry from the signal path, achieving equalizer frequency performance through the continuous-time linear equalizer alone. This extraction eliminates the power-consuming DFE components while maintaining signal quality through alternative continuous-time processing mechanisms.
Solution Approach 2:
The continuous-time linear equalizer serves as an intermediary that performs the equalization function without requiring the additional decision feedback equalizer circuitry. This intermediary approach achieves the same frequency performance through a different mechanism that consumes less power and has lower complexity.
3Productivity
If higher synchronization signal frequencies above 2.2 GHz to 3.2 GHz are used to increase data rate, then productivity is improved, but power consumption increases and timing alignment becomes more difficult
Solution Approach 1:
The patent implements dynamic continuous-time processing that adapts to higher frequencies without requiring additional power for delay compensation. The continuous-time linear equalizer naturally handles the timing adjustments needed at higher data rates through its continuous processing capability, eliminating the need for power-intensive discrete delay circuits that would be required at lower frequencies.
Data Source
AI summary
An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.