Semiconductor Memory Refresh Control Circuit Dual Period
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Solution Overview
Problem
Semiconductor memory devices face power consumption issues due to current leakage, leading to unstable charge storage in capacitors, which necessitates frequent refresh operations to maintain data accuracy, thereby increasing power usage.
Innovation Solution
A semiconductor memory device that selectively performs refresh operations based on the most significant high bit of the input address, distinguishing between a first refresh period for only active word lines and a second period for all word lines, thereby minimizing power consumption by skipping unnecessary refreshes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed on all word lines to ensure data retention, then data accuracy is maintained, but power consumption increases
Solution Approach 1:
The refresh operation is divided into two distinct phases: a first refresh period that selectively refreshes only active word lines (those with the most significant high bit matching the current refresh address), and a second refresh period that sequentially refreshes all word lines. This segmentation allows the system to optimize power consumption by performing minimal necessary refreshes during active periods while ensuring complete coverage during less active periods.
Solution Approach 2:
During the first refresh period, the system performs partial refresh action by selectively refreshing only the subset of word lines that are currently active (identified by matching the most significant high bit of the input address with the refresh address). This partial action is sufficient to maintain data accuracy for actively accessed memory regions while avoiding unnecessary power consumption from refreshing inactive regions.
2Duration of action of stationary object
If refresh operations are performed frequently to compensate for charge leakage, then data retention is improved, but current consumption increases
Solution Approach 1:
The refresh operation is structured as periodic action with two alternating periods. The first refresh period selectively refreshes active word lines based on address matching, while the second refresh period performs sequential refresh of all word lines. This periodic alternation ensures that data retention requirements are met through complete coverage in the second period, while the first period optimizes current consumption by refreshing only necessary active regions.
3Use of energy by moving object
If selective refresh of active word lines is performed, then power consumption is reduced, but data retention may be compromised
Solution Approach 1:
The invention merges two different refresh strategies into a unified dual-period refresh mechanism. The first refresh period implements selective refresh of active word lines to minimize power consumption, while the second refresh period implements sequential refresh of all word lines to ensure complete data retention coverage. By merging these two approaches and alternating them periodically, the system achieves both power efficiency and reliable data retention.
Data Source
AI summary
A semiconductor memory device includes a refresh counter generating a counting address that is sequentially increasing according to a refresh command; an active latch generating an active address corresponding to an input address according to an active command; and a refresh control circuit repeatedly performing a first refresh period and a second refresh period according to the refresh command, and controlling selective refresh of one or more word lines corresponding to the counting address selected based on one or more high bits of the active address during the first refresh period and controlling sequential refresh of the word lines corresponding to the counting address during the second refresh period.