High-Voltage Configuration Memory Cell for FPGA Reliability
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Solution Overview
Problem
Traditional configuration memory cells in FPGAs are unable to be written to or read from when powered up in a high-voltage domain, leading to performance issues and power consumption due to the need to power down and power up with different voltage levels.
Innovation Solution
The design of a memory cell that includes a pair of cross-coupled inverters with additional WordLines, allowing for two-phase write and read operations while maintaining high-voltage operation, thus preventing Single Event Upsets (SEUs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional configuration memory cells operate in high-voltage domain, then they can be written to and read from, but transistors experience excessive stress leading to Single Event Upsets (SEUs)
Solution Approach 1:
The memory cell is divided into two separate access paths: a first access path with first access transistors for high-voltage operations, and a second access path with second access transistors for low-voltage operations. This segmentation allows the cell to handle high-voltage reads while protecting transistors from excessive stress through the alternative low-voltage access path.
Solution Approach 2:
The patent introduces additional access transistors as intermediary elements between the bit line and the storage nodes. These intermediary transistors act as voltage regulators and protect the core memory transistors from direct high-voltage stress during write operations, while still enabling high-voltage domain operation.
2Adaptability or versatility
If memory cells require power cycling to switch voltage domains, then they can operate in both low-voltage and high-voltage domains, but performance deteriorates and power consumption increases
Solution Approach 1:
The memory cell is pre-configured with multiple access paths and transistor structures that enable direct voltage domain switching without requiring power cycling. The cell maintains the capability to operate in both low-voltage and high-voltage domains simultaneously, allowing the system to switch voltage domains in advance before operations begin.
Solution Approach 2:
The patent implements dynamic voltage domain operation by enabling the memory cell to switch between low-voltage and high-voltage modes based on operational requirements. The cell can dynamically adapt its operating voltage without physical reconfiguration or power cycling, improving performance and reducing latency.
3Reliability
If additional access transistors and WordLines are added to the memory cell, then high-voltage operation and SEU resistance are enabled, but device complexity increases
Solution Approach 1:
The additional access transistors and WordLines are designed to serve multiple functions: they enable high-voltage domain operation, provide SEU resistance, and maintain backward compatibility with low-voltage operations. This multi-functionality reduces the need for separate dedicated structures for each function.
Solution Approach 2:
The patent merges the high-voltage access functionality with the existing low-voltage access structure by sharing common storage nodes and incorporating additional access transistors into the existing cell architecture. This merging approach minimizes the increase in device complexity while achieving the desired reliability improvements.
Data Source
AI summary
An apparatus may include a first inverter, a second inverter, a first access transistor, and a second access transistor. The first inverter and a second inverter may be cross-coupled between a first node and a second node to store a signal state represented by voltage values at the first node and the second node. The first and second inverters may be configured to operate reliably under voltage conditions higher than a positive supply voltage of the apparatus. The first access transistor may selectively couple the first node to a bit line, and allow direct control of the first node during access operations. The second access transistor may selectively couple the second node to the bit line, and allow direct control of the second node during access operations. The respective positive supply inputs of the first inverter and the second inverter may be to couple to a voltage supply associated with a higher voltage level than the positive supply voltage of the apparatus.