SRAM Bitcell Back Gate Control for Write Margin and Read Speed
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Solution Overview
Problem
There is a need to improve the write time, write margin, and read speed of SRAM bitcells in SRAM devices, as existing technologies do not effectively optimize these parameters.
Innovation Solution
The implementation of a static random access memory (SRAM) bitcell circuit with direct connections between bitlines and the back gates of transistors in CMOS inverters, allowing potentials on bitlines to be applied to the back gates of transistors, and connections between wordlines and pass transistors' back gates, enhancing control over transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM bitcell structures are used, then device complexity is reduced, but write margin and read speed are insufficient
Solution Approach 1:
The bitcell is segmented into two distinct CMOS inverters (first inverter with first and second transistors, second inverter with third and fourth transistors) with independent back gate control. This segmentation allows separate optimization of write and read operations by independently controlling the back gates of different transistor pairs, thereby improving write margin without excessive complexity increase.
Solution Approach 2:
The patent introduces a new control dimension by utilizing back gate connections in addition to the conventional front gate control. By applying voltages to back gates (BG1, BG2, BG3, BG4) in addition to wordline and bitline signals, the patent creates an additional degree of freedom for controlling transistor operation, improving write margin and read speed while maintaining acceptable device complexity.
2Speed
If conventional SRAM bitcell structures are used, then manufacturing is simpler, but read speed is insufficient
Solution Approach 1:
The back gates of the transistors are pre-configured with specific voltage potentials before read operations commence. During read operations, the back gate voltages are adjusted in advance to optimize transistor conductivity and accelerate the read process, thereby improving read speed without significantly increasing structural complexity.
Solution Approach 2:
The patent implements dynamic back gate voltage control where the back gate potentials are adjusted based on the operational state (read, write, hold). This dynamic adjustment optimizes transistor performance for different operations, with specific back gate voltages applied during read operations to enhance read speed while maintaining manageable device complexity.
3Speed
If conventional SRAM bitcell structures are used, then power consumption is lower, but write speed is insufficient at low voltages
Solution Approach 1:
The patent changes the voltage parameters applied to back gates to optimize write operations at low supply voltages. By applying specific voltage potentials to back gates (e.g., BG3 and BG4 connected to bitlines, BG1 and BG2 to wordline), the transistors achieve enhanced conductivity that improves write speed at low voltages while maintaining reasonable power consumption levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves write margin for ultra-low voltage operation, read speed at all voltages, and write speed at low voltages, providing enhanced performance in SRAM bitcells.
Implementation Method 1
each transistor having a gate terminal and a back gate terminal... allowing potentials on bitlines to be applied to the back gates of transistors... enhancing control over transistor operation
Data Source
AI summary
An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.