Single MBIST Controller Via Network-On-Chip Bus
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Solution Overview
Problem
In integrated circuits, particularly field programmable gate arrays (FPGAs), using multiple configurable MBIST controllers for memory testing is time-consuming, resource-intensive, and difficult to meet at-speed frequency testing requirements, while also being costly due to the scattered nature of memory blocks and the need for extensive resources.
Innovation Solution
Implementing a single MBIST controller circuit that generates and transmits MBIST signals through a high-speed pipelined network-on-chip (NOC) bus to concurrently test multiple memory circuits, reducing the need for additional routing paths and resources by using the NOC for both configuration and MBIST signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple MBIST controllers are used to test scattered memory blocks, then memory testing coverage is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent applies universality by designing a single MBIST controller that can test multiple scattered memory blocks across different banks. The controller is configured to generate test patterns and control signals that can be routed to various memory locations through the interconnect fabric, eliminating the need for dedicated controllers for each memory block while maintaining comprehensive testing coverage.
Solution Approach 2:
The patent uses the interconnect fabric as an intermediary between the single MBIST controller and multiple memory blocks. The fabric routes control signals and test data from the controller to different memory banks, enabling one controller to efficiently manage tests across scattered memory locations without requiring direct point-to-point connections.
2Productivity
If multiple MBIST controllers are deployed, then testing parallelism is improved, but manufacturing cost and area usage increase
Solution Approach 1:
The patent merges the functionality of multiple MBIST controllers into a single unified controller. This consolidation reduces the total controller area while maintaining testing capabilities across all memory blocks. The single controller achieves parallelism by efficiently managing multiple test operations through the interconnect fabric rather than requiring physically separate controller instances.
3Reliability
If dedicated routing paths are created for MBIST signals, then signal transmission reliability is improved, but circuit area and resource consumption increase
Solution Approach 1:
The patent makes the interconnect fabric multi-functional by using it for both normal operational data transmission and MBIST signal routing. The fabric's existing routing resources are leveraged to carry test control signals and patterns to memory blocks, eliminating the need for dedicated MBIST routing paths while maintaining signal transmission reliability through the fabric's established communication channels.
4Device complexity
If a single MBIST controller is used, then resource consumption is reduced, but testing speed and frequency requirements become difficult to meet
Solution Approach 1:
The patent implements preliminary action by pre-configuring the interconnect fabric and memory banks for efficient test operation. Test patterns and control signals are prepared and routed in advance through the fabric, enabling the single MBIST controller to achieve high-speed testing by minimizing setup overhead and optimizing signal paths before actual testing begins.
Data Source
AI summary
An integrated circuit includes memory circuits, a selector circuit, a bus coupled to the selector circuit, and a controller circuit. The controller circuit provides test signals from the controller circuit through the bus to the selector circuit for transmission to the memory circuits during a memory built-in-self-test mode. Each of the memory circuits can include a comparator circuit configurable to compare a read data bit read from one of the memory circuits to an expected data bit in the test signals to generate a sticky error bit during the memory built-in-self-test mode.