Global Select Pin Time-Multiplexing for Memory Rank Access
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Solution Overview
Problem
As memory density increases in electronic devices, the number of pins required to access multiple memory ranks and ports becomes expensive and inefficient, particularly in devices with fixed pin requirements but needing higher memory capacity than single pin-per-rank or pin-per-port configurations.
Innovation Solution
The use of a single global Port Select pin or Chip Select pin to access multiple internal Port Select or Chip Select pins, reducing the external pin count by employing counter and comparator circuits to decode and activate specific internal pins, allowing full access to memory circuits with minimal external I/O pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple Chip Select pins are added to access additional memory ranks, then memory capacity is increased, but the number of external pins increases
Solution Approach 1:
The patent merges multiple Chip Select pins into a single shared pin that can be time-multiplexed to select different memory ranks. The counter circuit decodes the timing information to activate the appropriate internal CS pin, allowing one external pin to control multiple memory ranks that would traditionally require separate CS pins for each rank.
Solution Approach 2:
The patent introduces dynamic time-multiplexing where the single external CS pin changes its function over time based on counter decoding. Instead of having static dedicated pins for each memory rank, the system dynamically assigns the CS function to different internal pins based on timing signals generated by the counter circuit.
2Adaptability or versatility
If multiple Port Select pins are added to access multiple ports, then memory access capability is increased, but the number of external pins increases
Solution Approach 1:
The patent combines multiple Port Select pins into a single shared PS pin that is time-multiplexed to select different ports. The counter circuit tracks timing information and decodes it to activate the appropriate internal PS pin, enabling one external pin to control multiple ports that would traditionally require separate PS pins.
Solution Approach 2:
The system dynamically assigns the Port Select function to different internal pins based on timing signals. The single external PS pin is time-multiplexed, with the counter circuit generating timing information that dynamically selects which internal PS pin should be active at any given moment.
3Device complexity
If pin count is reduced to minimize I/O pins, then device complexity is decreased, but memory access capability is limited
Solution Approach 1:
The patent introduces counter circuits as intermediary components between the single external pin and the multiple internal pins. These counters decode timing information and generate the appropriate select signals to activate the correct internal CS or PS pin, enabling the single external pin to control multiple memory ranks and ports through time-multiplexing.
Solution Approach 2:
The system uses periodic timing signals generated by counter circuits to control the time-multiplexed access to different memory ranks and ports. The counters generate periodic decode signals that periodically activate different internal pins, enabling sequential access to multiple targets through a single external pin over time.
Data Source
AI summary
Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.