SRAM Cell Switching Circuit for Subthreshold Stability
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Solution Overview
Problem
SRAM cells operating in the subthreshold voltage region face reliability issues due to voltage and temperature variations, requiring enhanced write ability and stability for biomedical applications while maintaining low power consumption.
Innovation Solution
The SRAM cell design incorporates a latch unit with a bi-inverting circuit and a switching circuit, utilizing a reverse short channel effect and high-threshold-voltage components to enhance write ability, reduce threshold voltage variations, and decouple the data storage node from the bitline, thereby improving read stability and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the SRAM cell operates in the subthreshold voltage region to achieve low power consumption, then power consumption is reduced, but reliability and stability deteriorate due to voltage and temperature variations
Solution Approach 1:
The patent changes the operating voltage parameter to the subthreshold region to achieve ultra-low power consumption. It compensates for the resulting reliability degradation by adjusting device dimensions (channel width-to-length ratio) and using high-threshold-voltage transistors in the latch circuit to maintain stability despite voltage and temperature variations.
Solution Approach 2:
The patent applies different transistor threshold voltages to different parts of the circuit. High-threshold-voltage transistors are used specifically in the latch circuit where stability is critical, while other parts can use lower threshold voltages to maintain performance. This local differentiation allows the circuit to operate stably in the subthreshold region.
2Stability of the object's composition
If the positive feedback of the storage node is maintained for data latching, then data hold stability is improved, but write ability deteriorates due to feedback interference during write operations
Solution Approach 1:
The patent makes the feedback path dynamic by controlling the switch transistor. During write operations, the switch transistor is turned off to disconnect the positive feedback path, allowing external write signals to override the latched data. During read and hold operations, the switch is turned on to establish the feedback path for stable data retention. This dynamic switching resolves the contradiction between write ability and data hold stability.
3Ease of operation
If the data storage node is connected to the bitline for read operations, then read access is enabled, but read stability deteriorates due to coupling effects
Solution Approach 1:
The patent introduces a switch transistor as an intermediary between the data storage node and the bitline. This intermediary allows controlled connection during read operations while providing isolation during write and hold operations. The switch acts as a gatekeeper that enables read access when needed while preventing harmful coupling effects that would degrade read stability.
4Ease of manufacture
If conventional SRAM cell architecture is used, then manufacturing is simplified, but susceptibility to soft errors and half-selected disturbances increases
Solution Approach 1:
The patent segments the wordline selection by using complementary wordlines (WL and WLb) that control different sets of access transistors. This segmentation ensures that when one wordline is active, the other is inactive, preventing half-selected cell disturbances. The bit-interleaving architecture further segments the memory array to isolate soft errors to individual cells rather than affecting multiple cells simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves stable operation and enhanced write ability in the subthreshold region, reducing power consumption and improving reliability by cutting off positive feedback during writes and utilizing bit-interleaving architecture to mitigate soft errors and half-selected disturbances.
Implementation Method 1
when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit
Implementation Method 2
Each of the read/write transistors utilizes a reverse short channel effect for the SRAM cell to enhance the read/write ability and reduce the variation degree of the threshold voltage resulting from the manufacturing process
Data Source
AI summary
A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.