Semiconductor Device DLL ODT Delay Line Segmentation
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Solution Overview
Problem
Conventional semiconductor devices with On Die Termination (ODT) function suffer from increased power consumption due to the active state of the Delay Locked Loop (DLL) circuit during ODT operation, which affects signal quality and data transfer rates.
Innovation Solution
The implementation of a DLL circuit with a first delay line and an ODT circuit featuring a second delay line set to an equivalent delay amount by the DLL circuit, allowing ODT operation while keeping the DLL circuit inactive, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit is kept active during ODT operation to ensure proper timing, then timing synchronization is maintained, but power consumption increases
Solution Approach 1:
The patent segments the delay line functionality into two independent parts: the original DLL delay line and a replica delay line. The replica delay line is specifically dedicated to ODT operation, allowing the main DLL circuit to be deactivated while maintaining timing functionality during ODT mode. This segmentation enables independent control of timing resources.
Solution Approach 2:
The patent creates a replica delay line that copies the delay characteristics of the original DLL delay line. This replica is configured to match the delay amount of the first delay line, enabling it to perform timing functions independently during ODT operation without requiring the main DLL circuit to remain active.
2Device complexity
If the ODT operation is performed without a replica delay line using the main DLL delay line, then the device complexity is reduced, but the DLL circuit must remain active increasing power consumption
Solution Approach 1:
The patent segments the delay line functionality into two independent parts: the original DLL delay line and a replica delay line. The replica delay line is specifically dedicated to ODT operation, allowing the main DLL circuit to be deactivated while maintaining timing functionality during ODT mode. This segmentation enables independent control of timing resources.
Solution Approach 2:
The patent creates a replica delay line that copies the delay characteristics of the original DLL delay line. This replica is configured to match the delay amount of the first delay line, enabling it to perform timing functions independently during ODT operation without requiring the main DLL circuit to remain active.
Data Source
AI summary
A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.