Semiconductor Memory Redundancy Cell Testing Controller
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Solution Overview
Problem
Conventional semiconductor memory devices can only test fuse-programmed redundancy cells, making it impossible to check all redundancy cells for defects, which can lead to unreliable repair operations due to the substitution of defective redundancy cells for other defective cells.
Innovation Solution
A semiconductor memory device that allows for the testing of all redundancy cells using an external command signal and address signal, incorporating a command decoder, redundancy cell test controller, and redundancy decoder to select and test redundancy cells independently of fuse programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fuse programming circuit is used to test redundancy cells, then fuse-programmed redundancy cells can be tested, but non-fuse-programmed redundancy cells cannot be tested
Solution Approach 1:
The test operation controller is designed to provide universal testing capability for both fuse-programmed and non-fuse-programmed redundancy cells. By receiving precharge signals and generating test operation control signals, the controller can selectively activate different testing modes to cover all redundancy cell types, making the testing system multi-functional and adaptable to various redundancy configurations.
Solution Approach 2:
The testing system dynamically switches between different operation modes based on the type of redundancy cells being tested. The controller can transition from fuse programming mode to test operation mode by detecting precharge signals, enabling flexible adaptation to different testing requirements without requiring separate dedicated circuits for each redundancy cell type.
2Reliability
If all redundancy cells are tested, then defective cells can be identified and substituted reliably, but the device complexity increases
Solution Approach 1:
The testing system utilizes existing circuit resources within the semiconductor memory device to perform redundancy cell testing. By leveraging the precharge signal mechanism and existing decoder circuits, the system achieves comprehensive testing functionality without requiring extensive external testing equipment or adding significant complexity to the device architecture.
Solution Approach 2:
The test operation controller is integrated with the existing fuse programming circuit and decoder structures. By merging the testing functionality with existing circuitry, the patent achieves comprehensive redundancy cell testing while minimizing the increase in device complexity. The same control signals and circuit paths are used for both programming and testing operations.
Data Source
AI summary
Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells. This increases the reliability of a repair operation.