Tipped RRAM Interface for Localized Filament Control
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Solution Overview
Problem
Existing RRAM cells face challenges in scaling down due to random formation of conductive filaments and edge effects, which affect the reliability and efficiency of memory operations.
Innovation Solution
The formation of tipped structures at the interface between insulator and conductor layers helps to focus the electric field, localizing the formation of conductive filaments and reducing the operating voltage of RRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RRAM cell structures are used, then manufacturing is simpler, but conductive filaments form randomly reducing reliability
Solution Approach 1:
The patent applies local quality by creating tipped structures at specific locations within the RRAM cell where conductive filaments are desired. These tips are formed by selectively removing material to create localized geometric features that concentrate electric fields. By making the structure non-uniform with specific tipped regions, the patent ensures that conductive filaments form preferentially at these controlled locations rather than randomly throughout the cell, thereby improving reliability while maintaining reasonable manufacturing complexity.
2Productivity
If RRAM cells are scaled down, then device density increases, but edge effects become more significant reducing efficiency
Solution Approach 1:
The patent addresses edge effects in scaled-down devices by introducing localized tipped structures that dominate the electric field distribution. These tips create strong localized field concentrations that override the influence of device edges and boundaries. By concentrating the electric field at specific internal points rather than allowing it to distribute along edges, the patent enables efficient operation even at reduced device dimensions, thereby maintaining productivity while mitigating harmful edge effects.
3Use of energy by moving object
If conventional structures are used, then manufacturing is easier, but operating voltage remains high
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the RRAM cell structure through the formation of tipped features. By changing the shape parameter (creating tips with smaller radius of curvature), the electric field distribution is fundamentally altered. These geometric parameter changes lead to higher electric field concentrations at the tips, which enable conductive filament formation at lower applied voltages. The manufacturing process remains relatively simple using standard etching and deposition techniques, achieving lower operating voltage without significantly compromising ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and efficiency of RRAM cells by preferentially forming conductive filaments at the tipped structures, allowing for lower operating voltages and improved scalability.
Implementation Method 1
isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer
Implementation Method 2
each having concave sidewall surfaces that meet at an interface between the insulator layer and the conductor layer to form a tip to focus electrical field strength
Data Source
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AI summary
Methods of forming a settable resistance device, settable resistance devices, and neuromorphic computing devices include isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots in exposed sidewalls of the insulator layer, thereby forming a tip at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is between the electrode and the tip.