Memory Controller Scaling Request Bandwidth with Data Granularity
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Solution Overview
Problem
The increasing demand for higher data bandwidth in advanced computing systems poses a challenge due to the bandwidth bottleneck caused by the reduction in the number of pins available for data transfer in memory systems, which limits the ability to access large amounts of data efficiently.
Innovation Solution
The development of a memory device and system with multiple request (RQ) ports that scale with data (DQ) bandwidth using point-to-point topologies and signaling rates, allowing for capacity scaling while maintaining low or constant access granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory chips is reduced to increase density, then storage capacity is improved, but the number of pins available for data transfer is reduced, causing bandwidth bottleneck
Solution Approach 1:
The patent divides the memory system into multiple independent memory devices, each with its own request port. Instead of using a single high-density chip with limited pins, the system segments storage across multiple chips (e.g., 8 chips of 1Gb each to achieve 8Gb capacity), allowing each chip to have adequate pin availability for high-speed data transfer. This segmentation resolves the contradiction by maintaining both high storage capacity and sufficient bandwidth through parallel access to multiple devices.
2Quantity of substance
If high density memory chips are used, then storage capacity increases, but the number of pins for data transfer decreases, limiting bandwidth
Solution Approach 1:
The patent transitions from a single-dimension approach (one chip with limited pins) to a multi-dimensional architecture by adding the dimension of parallelism across multiple memory devices. Each device operates independently with its own request port, creating a scalable system where capacity and bandwidth both increase with the number of devices. This dimensional expansion allows the system to achieve 8Gb capacity while maintaining high bandwidth through simultaneous data transfer across multiple parallel channels.
3Quantity of substance
If multiple memory devices are used to increase capacity, then storage capacity is improved, but request bandwidth may become bottlenecked without multiple request ports
Solution Approach 1:
The patent implements request ports that are universal and scalable across multiple memory devices. Each memory device is equipped with its own request port, allowing the controller to issue requests to multiple devices simultaneously. This multi-functional request interface enables the system to scale capacity by adding devices while maintaining request bandwidth, as each device can be accessed independently without contending for shared request resources.
Data Source
AI summary
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.