Memory Data Path Segmentation for Layout Area Reduction

Solution Overview

Problem

Conventional memory devices with numerous circuit elements in their data paths face challenges such as increased circuit layout area and reduced transfer speed, which affect their performance and control.

Innovation Solution

The memory device employs a data path circuit configuration with transfer circuit units and driver circuit units that selectively transfer and serialize data signals, using a '4n' prefetch architecture and counters to manage signal activation, thereby optimizing circuit layout and transfer speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a large number of circuit elements are used in a circuit path, then the memory device can handle more data, but the circuit layout area increases and transfer speed decreases

Engineering Contradiction:

Improvenumber of circuit elementsVSAvoidcircuit layout area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The circuit path is divided into multiple stages, with each stage containing a limited number of circuit elements. Transfer circuit units are segmented into multiple components (first transfer circuit unit, second transfer circuit unit, third transfer circuit unit) that operate in sequence. This segmentation allows data to be processed in smaller chunks across multiple stages rather than requiring all circuit elements to be present in a single path, thereby reducing the layout area while maintaining data handling capacity.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If a large number of circuit elements are used in a circuit path, then the memory device can handle more data, but the transfer speed decreases

Engineering Contradiction:

Improvenumber of circuit elementsVSAvoidtransfer speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The circuit path is divided into multiple stages, with each stage containing a limited number of circuit elements. Transfer circuit units are segmented into multiple components (first transfer circuit unit, second transfer circuit unit, third transfer circuit unit) that operate in sequence. This segmentation allows data to be processed in smaller chunks across multiple stages rather than requiring all circuit elements to be present in a single path, thereby reducing the layout area while maintaining data handling capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory device employs a '4n' prefetch architecture that preliminarily loads data into the circuit path before it is actually needed for transfer. By pre-fetching data in advance and staging it in the memory device, the system prepares data for rapid transmission when required, thereby maintaining high transfer speeds despite the segmented circuit architecture.

Inventive Principle:

Principle #10Preliminary action

3Quantity of substance

If many circuit elements are used in a circuit path, then data capacity increases, but circuit control becomes more challenging

Engineering Contradiction:

Improvenumber of circuit elementsVSAvoidcircuit control

Core Design Contradiction:

Quantity of substanceVSEase of operation

Solution Approach 1:

The circuit path is divided into multiple stages, with each stage containing a limited number of circuit elements. Transfer circuit units are segmented into multiple components (first transfer circuit unit, second transfer circuit unit, third transfer circuit unit) that operate in sequence. This segmentation allows data to be processed in smaller chunks across multiple stages rather than requiring all circuit elements to be present in a single path, thereby reducing the layout area while maintaining data handling capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory device employs a '4n' prefetch architecture that preliminarily loads data into the circuit path before it is actually needed for transfer. By pre-fetching data in advance and staging it in the memory device, the system prepares data for rapid transmission when required, thereby maintaining high transfer speeds despite the segmented circuit architecture.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8023340B2Signal transfer apparatus and methods

Publication Date: 2011.09.20 MICRON TECHNOLOGY INC

AI summary

Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.