Memory Device Bad Column Repair Logic Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory devices face inefficiencies due to the need for redundant columns to replace bad columns, which occupy additional circuit areas and are only available on a sub-plane basis, making them inefficient for full-plane operations.
Innovation Solution
A memory device with a repair logic circuit that receives a bad column table to map data accordingly, allowing for full-plane-based bad column repair, reducing redundancy and enhancing circuit area efficiency by managing bad columns across the entire plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant columns are incorporated on a sub-plane basis to replace bad columns, then bad column repair capability is provided, but additional circuit areas are occupied and efficiency is reduced
Solution Approach 1:
The patent implements a universal bad column repair mechanism that operates across the entire memory plane rather than being restricted to sub-planes. The repair logic circuit receives bad column information from any location in the memory array and performs remapping operations globally, allowing redundant columns to serve the entire plane instead of being confined to specific sub-planes. This multi-functional approach enables the same repair infrastructure to handle bad columns throughout the complete memory device.
Solution Approach 2:
The patent merges the repair functionality across the entire memory plane by integrating the repair logic circuit to handle bad columns from all sub-planes centrally. Instead of having separate repair mechanisms for each sub-plane, the system combines the repair operations into a unified process that manages bad columns plane-wide, thereby reducing the total circuit area required for redundancy while maintaining comprehensive repair capability.
2Reliability
If redundant columns are incorporated on a sub-plane basis, then bad column replacement is enabled, but efficiency is reduced due to limited availability
Solution Approach 1:
The repair logic circuit is designed with universal functionality to handle bad columns from any sub-plane within the entire memory plane. The circuit receives bad column information regardless of its origin location and performs remapping operations that are valid across the complete plane, thereby maximizing the utilization of redundant columns and improving overall repair efficiency compared to sub-plane restricted approaches.
Solution Approach 2:
The system performs preliminary identification and recording of bad columns across the entire memory plane during manufacturing or initial operation. The repair logic circuit maintains a comprehensive bad column table that contains information about all defective columns in the plane, allowing efficient remapping operations to be performed without needing to scan or identify bad columns during normal operation, thereby improving repair efficiency.
3Area of stationary object
If full-plane-based bad column repair is implemented, then circuit area efficiency is enhanced, but complexity of managing bad columns across the entire plane increases
Solution Approach 1:
The repair logic circuit serves as an intermediary component that manages bad column information and coordinates remapping operations across the entire memory plane. This centralized mediator receives bad column information from the memory array, processes the remapping logic, and outputs corrected data to the buffer, thereby simplifying the overall system architecture despite the plane-wide scope of operation. The intermediary structure reduces complexity by providing a single point of control rather than distributed management across multiple sub-planes.
Solution Approach 2:
The system uses a bad column table that stores copies of bad column information from the entire memory plane in a centralized location within the repair logic circuit. By maintaining this informational copy, the system can perform remapping operations based on the stored data without needing to continuously access or manage the physical bad columns throughout the plane, thereby reducing management complexity while maintaining full-plane repair capability.
Data Source
AI summary
A memory device includes a memory array, a first buffer, a second buffer, a repair logic circuit and an internal memory. The method of operating the memory device includes: the repair logic circuit receiving a bad column table from the internal memory, the bad column table containing information of a bad column in the memory array; the first buffer receiving first data; the repair logic circuit receiving the first data from the first buffer; and the repair logic circuit mapping the first data onto second data according to the bad column table.