DLL Circuit Lock-Hold Control for Lower Timing Power
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Solution Overview
Problem
Existing DLL circuits struggle to achieve sufficient power saving while maintaining precise timing control, as they continue to operate in a delay-locked state with controlled delay amounts.
Innovation Solution
The DLL circuit incorporates a first delay line with a delay buffer, a control voltage generation unit, a charge storage unit, and a drive control unit. The drive control unit stops the phase comparator operation once the delay-locked state is determined, allowing the control voltage to be held and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase comparator continues to operate to maintain delay-locked state, then timing control precision is improved, but power consumption increases
Solution Approach 1:
The phase comparator operates periodically rather than continuously. A determination unit detects whether the DLL circuit is in a delay-locked state, and a drive control unit stops the phase comparator operation when locked. This periodic operation mode maintains timing control precision when needed while reducing power consumption during stable operation.
Solution Approach 2:
The system dynamically adjusts the operation state of the phase comparator based on the delay-locked state detection. The drive control unit changes the operational status of the phase comparator from active to stopped state according to real-time feedback, optimizing the balance between precision and power consumption.
2Use of energy by moving object
If the DLL circuit is activated for power saving, then power consumption is reduced, but timing control capability is lost
Solution Approach 1:
The DLL circuit monitors its own delay-locked state through the determination unit and automatically controls the phase comparator operation through the drive control unit. This self-service mechanism ensures the circuit maintains timing control capability when needed while autonomously entering low-power mode when stable, without external intervention.
Solution Approach 2:
The determination unit continuously monitors the delay-locked state and provides feedback to the drive control unit, which adjusts the phase comparator operation accordingly. This feedback loop ensures timing control capability is maintained when the system transitions between active and low-power states.
Data Source
AI summary
A DLL circuit includes: a first delay line having a first delay buffer that provides a delay corresponding to a control voltage to an input clock signal and configured to output an output clock signal via the first delay buffer; a control voltage generation unit having a phase comparator that compares phases of the input clock signal and the output clock signal, and configured to generate the control voltage based on an output of the phase comparator; a charge storage unit configured to store charges for holding the control voltage; and a drive control unit configured to output a drive control signal for stopping an operation of the phase comparator based on a determination result regarding a delay-locked state.