DLL Locking State Detection for Clock Jitter Stability
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Solution Overview
Problem
DLL circuits in semiconductor ICs face instability due to frequent changes in the locking state signal caused by jitter in the external clock signal, leading to unstable internal clock generation and reduced operational stability.
Innovation Solution
A locking state detector that compares reference and feedback clock signals to generate distinct phase difference signals, enabling a locking state signal only when the phase difference is below a first range and disabling it when it exceeds a wider second range, thereby maintaining a stable operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the locking state detector disables the locking state signal whenever the phase difference exceeds a predetermined range due to jitter, then the phase difference can be corrected, but the locking state signal frequently changes causing unstable operation
Solution Approach 1:
The patent changes the threshold parameter from a single fixed value to multiple tiered values (first threshold and second threshold). When phase difference exceeds the first threshold, the detector generates a phase difference signal to adjust delay. When it exceeds the wider second threshold, the locking state signal is disabled. This parameter differentiation allows the system to tolerate normal jitter while maintaining stability.
Solution Approach 2:
The patent segments the phase difference response into distinct zones using multiple thresholds. The first threshold zone handles normal phase adjustments, while the second threshold zone handles extreme deviations. This segmentation prevents over-reaction to minor jitter and maintains stable operation by only disabling the locking state signal for significant phase errors.
2Manufacturing precision
If the locking state signal is frequently changed due to jitter, then the phase difference can be continuously corrected, but the internal clock signal cannot be stably generated
Solution Approach 1:
The patent introduces a hierarchical threshold structure where the first threshold is tighter for precision control and the second threshold is wider for stability protection. This parameter change allows the system to achieve phase synchronization through the first threshold while preventing instability by using the second threshold as a protection boundary that rarely triggers.
Solution Approach 2:
The patent applies partial action by using two different response levels instead of a single full-disability response. For minor phase errors (below second threshold), the system applies partial correction through delay adjustment. For extreme errors (above second threshold), it applies excessive action by disabling the locking state signal to prevent instability, thus avoiding frequent unnecessary changes.
Data Source
AI summary
A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.