Multi-Phase Memory Clock Generator with DLL Skew Correction
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Solution Overview
Problem
Existing multi-phase clock generators for memory devices are complex and power-intensive, occupying large areas due to complicated multi-phase detectors, which complicates the correction of skew between multi-phase clocks.
Innovation Solution
A multi-phase clock generator with a reduced complexity structure, utilizing a delay locked loop (DLL) to correct duty errors and phase differences, incorporating variable delay lines, phase splitters, and duty cycle detectors to generate a 4-phase clock with accurate phase relationships, thereby reducing power consumption and area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional multi-phase clock generator is used, then multi-phase clock signals can be generated, but the device occupies large area and consumes high power due to complicated multi-phase detectors
Solution Approach 1:
The patent extracts and removes the complicated multi-phase detector from the clock generator architecture. Instead of using a traditional multi-phase detector to generate multi-phase clock signals, the invention uses a simplified phase detector combined with separate delay lines for each phase, thereby reducing area occupancy while maintaining multi-phase clock generation capability.
Solution Approach 2:
The patent segments the clock generation function into multiple independent delay lines (first delay line, second delay line, third delay line, fourth delay line), each responsible for generating a specific phase. This segmentation allows each delay line to be optimized independently and reduces the complexity of the overall system compared to a unified multi-phase detector approach.
2Reliability
If a conventional multi-phase clock generator is used, then multi-phase clock signals can be generated, but the device consumes high power due to complicated multi-phase detectors
Solution Approach 1:
The patent extracts and removes the power-intensive multi-phase detector from the architecture. By replacing it with simpler phase detectors and independent delay lines, the invention significantly reduces power consumption while maintaining the ability to generate accurate multi-phase clock signals.
Solution Approach 2:
The segmentation into four independent delay lines allows each line to operate with optimized power consumption for its specific phase generation task, rather than powering a complex multi-phase detector that must handle all phases simultaneously. This modular approach reduces overall power consumption.
3Reliability
If a conventional multi-phase clock generator is used, then multi-phase clock signals can be generated, but the correction of skew between multi-phase clocks becomes complicated
Solution Approach 1:
The patent segments the skew correction function into individual delay adjustment mechanisms for each delay line. Each delay line can be independently adjusted to correct skew for its specific phase, simplifying the overall skew correction process compared to a complex multi-phase detector that must handle all phase skew corrections simultaneously.
Solution Approach 2:
The patent introduces variable delay lines with adjustable delay amounts that can be dynamically controlled. The delay controller can adjust the delay of each delay line independently to correct phase skew, providing a flexible and simple mechanism for skew correction without requiring complex multi-phase detection and adjustment circuitry.
Data Source
AI summary
A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.