Delay-Locked Loop Phase Filtering for Noise-Resistant Locking
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in semiconductor devices face reliability issues due to noise in the phase comparing result, leading to undesired locking of the feedback clock and potential malfunctions, especially under power noise conditions.
Innovation Solution
The proposed DLL incorporates a filtering unit that generates a filtering signal based on the phase signal, updating it when the difference between lead and lag counts reaches a filtering depth, and a locking unit that activates the locking signal using different methods in high speed and low speed modes, with a control unit adjusting the delay value to maintain synchronization and reduce noise-related malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the phase comparing result is used directly to control the delay unit, then the DLL responds quickly to phase differences, but noise causes undesired locking and malfunctions
Solution Approach 1:
The patent applies preliminary action by counting the number of times the phase comparing result changes state before triggering a lock. The counter accumulates changes over a predetermined period, and only when the count reaches a threshold does the lock activate. This preliminary counting action filters out noise-induced false changes while preserving genuine phase synchronization events, thus improving reliability without significantly compromising response speed.
2Reliability
If noise filtering is applied to the phase signal, then malfunction occurrence is reduced, but the complexity of the DLL increases
Solution Approach 1:
The patent introduces a counter as an intermediary element between the phase comparing unit and the locking unit. This counter mediates the interaction by accumulating state changes and only triggering the lock when a predetermined count is reached. The intermediary counter effectively filters noise without requiring complex filtering circuits, thus improving reliability while minimizing increases in device complexity.
3Device complexity
If a single locking method is used for both high and low speed modes, then the device complexity is reduced, but the locking reliability in different speed modes is compromised
Solution Approach 1:
The patent applies dynamics by implementing different locking methods adapted to different operating conditions. In high-speed modes, one locking method is employed that is optimized for faster response, while in low-speed modes, a different locking method is used that prioritizes precision and noise filtering. This dynamic adaptation to operating conditions ensures high locking reliability across all speed modes without requiring an overly complex unified control mechanism.
Data Source
AI summary
A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.