Delay Locked Loop Phase Control for Voltage-Induced Latency Jumps
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Solution Overview
Problem
Delay locked loop devices are affected by latency jumps due to unstable external voltages, leading to timing drifts and challenges in maintaining a fixed timing relationship between signals.
Innovation Solution
The delay locked loop device incorporates a frequency detection and control circuit to dynamically adjust the phase detector's activation period based on the operating frequency of the memory device, detecting phase differences between reference and feedback clock signals to mitigate latency jumps caused by fluctuations in external power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase detector operates continuously to detect phase differences, then timing accuracy is improved, but power consumption increases and latency jumps occur due to unstable external voltages
Solution Approach 1:
The phase detector is activated periodically based on the operating frequency of the memory device rather than continuously. The activation period is dynamically adjusted according to frequency detection results, allowing the system to maintain timing accuracy while reducing power consumption and avoiding latency jumps caused by continuous operation under unstable voltage conditions
Solution Approach 2:
The system dynamically adjusts the activation period of the phase detector based on real-time frequency detection. This dynamic adaptation allows the phase detector to operate optimally under varying frequency and voltage conditions, maintaining measurement precision while avoiding the reliability issues associated with fixed continuous operation
2Measurement precision
If the phase detector is activated frequently to maintain timing accuracy, then phase detection precision is improved, but latency jumps occur due to unstable external voltages
Solution Approach 1:
Instead of frequent continuous activation, the phase detector is activated periodically with dynamically adjusted intervals. This periodic operation maintains phase detection precision by sampling at optimal intervals while reducing the cumulative latency impact of frequent activations under unstable voltage conditions
Solution Approach 2:
The system uses frequency detection feedback to control the activation timing of the phase detector. By monitoring the operating frequency and adjusting the activation period accordingly, the system maintains detection precision while optimizing the timing to minimize latency accumulation
3Stability of the object's composition
If continuous phase detection is performed to maintain fixed timing relationship, then timing stability is improved, but power consumption increases and latency jumps occur
Solution Approach 1:
The phase detector operates periodically rather than continuously, with activation periods dynamically adjusted based on frequency detection. This maintains timing relationship stability through regular sampling while significantly reducing power consumption by keeping the detector inactive during non-critical periods
Solution Approach 2:
The system uses its own frequency detection capability to automatically control the phase detector activation schedule. This self-regulating mechanism maintains timing stability while optimizing power consumption without requiring external control signals
Data Source
AI summary
A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.