Delay Locked Loop Phase Comparison Shift to Avoid Lock Errors
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Solution Overview
Problem
Delay locked loop circuits in semiconductor integrated circuits face malfunctions due to constant phase errors, which prevent the generation of desired frequencies and correct lock operations, especially with the increasing speed of semiconductor devices.
Innovation Solution
A control circuit is placed outside the delay locked loop, generating a control signal to shift the phase comparison relation between the reference signal and the output signal by a predetermined cycle, ensuring the timing of the reference signal input to the delay line matches the input timing to the phase comparator, thereby avoiding constant phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the delay locked loop circuit operates at high speeds to increase productivity, then the operating clock speed increases, but constant phase errors occur causing malfunction
Solution Approach 1:
A control signal is introduced as an intermediary element that mediates between the reference signal and the phase comparator. This control signal adjusts the timing of phase comparison operations to occur at appropriate cycles, preventing constant phase errors while maintaining high-speed operation capability
2Device complexity
If the phase comparison timing is not properly controlled, then the circuit structure remains simple, but constant phase errors occur preventing correct lock operation
Solution Approach 1:
The control signal is generated in advance based on the reference signal timing to pre-determine the appropriate phase comparison cycles. This preliminary timing control ensures that phase comparisons occur at correct intervals before potential errors can accumulate, maintaining reliability without complex additional circuitry
Data Source
AI summary
A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.