Delay-Locked Loop Clock Edge Delay for Stable Power-Down Recovery
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Solution Overview
Problem
The existing DLL circuits in semiconductor memory devices face challenges in maintaining accurate phase synchronization during frequent entries and exits from power down mode due to short clock enable signal periods, leading to asynchronous delay values and distorted data transmission.
Innovation Solution
A DLL circuit with a power down mode controller and a clock edge delay unit that generates a delayed control signal to allow sufficient time for phase update, preventing erroneous locking and ensuring accurate phase synchronization by delaying the clock edge when entering power down mode and enabling rapid recovery when exiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL circuit enters power down mode rapidly to reduce power consumption, then power saving is improved, but phase synchronization accuracy deteriorates due to insufficient time for phase update
Solution Approach 1:
The patent applies preliminary action by predicting when power down mode transitions will occur and pre-adjusting the delay line settings before the actual transition. The controller predicts future power down entries based on clock enable signal patterns and proactively configures the delay line to appropriate delay values, ensuring phase synchronization is already prepared before the mode switch occurs. This prevents synchronization errors that would otherwise occur during rapid transitions.
Solution Approach 2:
The patent implements dynamics by making the delay line configuration adaptive and variable rather than fixed. The delay line controller dynamically adjusts delay values based on the predicted power mode transitions and current operating conditions. The system can switch between different delay configurations rapidly, allowing the phase synchronization to adapt to changing power states without loss of accuracy.
2Productivity
If the clock enable signal period is shortened to allow frequent power down mode transitions, then productivity is improved, but phase update accuracy deteriorates
Solution Approach 1:
The controller performs preliminary phase update preparation by predicting power mode transitions and configuring the delay line in advance. This pre-action allows the phase update to be effectively completed even when the clock enable signal period is very short, maintaining accuracy despite rapid transitions and high productivity requirements.
Solution Approach 2:
The system applies beforehand cushioning by maintaining a buffer of predicted transition information and pre-configured delay values. This cushioning effect provides a safety margin that ensures phase update accuracy is maintained even when external timing constraints are tight, protecting against synchronization errors during rapid mode transitions.
3Measurement precision
If the delay line is continuously updated to maintain synchronization, then phase synchronization accuracy is improved, but power consumption increases during power down mode
Solution Approach 1:
The patent extracts the delay line update operation from continuous execution and selectively applies it only when necessary. By predicting power mode transitions, the system extracts and performs updates only during appropriate timing windows, avoiding continuous updates during power down mode. This reduces power consumption while maintaining synchronization accuracy through targeted, predictive update scheduling.
Solution Approach 2:
The system implements periodic action by scheduling delay line updates at specific intervals based on predicted power mode transitions rather than continuously. The controller periodically reconfigures the delay line according to anticipated mode changes, maintaining synchronization accuracy while allowing power savings during stable power states by eliminating unnecessary continuous update operations.
Data Source
AI summary
A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.