Delay-Locked Loop Power Gating for Faster Memory Clock De-Skew
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Solution Overview
Problem
Conventional delay-locked loops have high power consumption and slow lock times, which hinder efficient clock signal de-skewing in memory systems.
Innovation Solution
A delay-locked loop circuit with reduced power consumption, lower latency, and faster lock time is implemented by selectively activating and deactivating memory devices, using a parallel structure for clock de-skewing that includes delay circuitry, code generation, and duty-cycle correction to minimize jitter and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional delay-locked loop is used for clock de-skewing, then clock signal timing can be adjusted, but power consumption is high and lock time is slow
Solution Approach 1:
The delay-locked loop is activated periodically or on-demand rather than continuously. The controller enables the DLL circuitry only when clock de-skewing is needed (e.g., during memory operations requiring precise timing) and disables it during idle periods, achieving both fast lock time (when activated) and reduced power consumption (when deactivated).
Solution Approach 2:
The system dynamically transitions the delay-locked loop between active and inactive states based on operational requirements. The controller monitors timing needs and adjusts the DLL power state accordingly, optimizing the balance between lock time performance and power consumption.
2Measurement precision
If delay-locked loop is continuously active to maintain precise timing, then clock de-skewing accuracy is maintained, but power consumption increases
Solution Approach 1:
The delay-locked loop is pre-configured with initial delay settings and calibration data stored in memory. When activated, it can quickly establish accurate clock de-skewing without requiring lengthy real-time calibration, enabling both high precision and low power consumption by minimizing the duration of active operation.
Solution Approach 2:
The system uses stored calibration patterns and delay settings that were previously established when the DLL was active. These copied configurations allow rapid reactivation with accurate timing without requiring the full calibration sequence to run again, maintaining precision while reducing active time and power consumption.
3Measurement precision
If delay circuitry is added to reduce clock skew, then timing precision improves, but device complexity increases
Solution Approach 1:
The delay-locked loop circuitry is designed to serve multiple functions: clock de-skewing, timing adjustment, and phase alignment. By consolidating these functions into a single multi-functional block, the patent reduces overall device complexity compared to implementing separate circuits for each function while maintaining high timing precision.
Solution Approach 2:
The delay elements, phase detectors, and control logic are merged into an integrated delay-locked loop module. This consolidation reduces the number of discrete components and interconnections required, simplifying the overall device architecture while providing precise clock timing control.
Data Source
AI summary
Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.