DLL-Based PWM Timing for Sub-Clock Resolution
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Solution Overview
Problem
Conventional pulse-width modulation (PWM) systems in digital signal processors have limited resolution due to system clock frequency constraints, making it difficult to achieve high-resolution PWM without requiring excessive clock frequencies or user calibration, which is unreliable and power-intensive.
Innovation Solution
A high-precision pulse-width modulation system utilizing a delay-locked loop (DLL) with a digital delay line and control circuitry that calibrates delays to the system clock, allowing for continuous self-calibration and reducing the need for user intervention, and splits the DLL into multiple stages to share resources across PWM channels, thereby increasing resolution and reducing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PWM with system clock frequency is used, then the implementation is simple and power consumption is low, but the resolution is limited to the clock period (e.g., 2 ns at 500 MHz)
Solution Approach 1:
The system segments the PWM generation function into two parts: a conventional PWM generator that operates at system clock frequency, and a separate high-precision delay unit that provides sub-clock-period resolution. This segmentation allows the system to achieve high resolution (150 ps) without requiring the entire system to operate at the high frequency (8 GHz+) that would be needed for conventional PWM alone.
2Measurement precision
If MEP technology is used to achieve high-resolution PWM, then the resolution can be improved to sub-clock period levels, but the step-size varies with process, voltage, and temperature making it unreliable
Solution Approach 1:
The system incorporates a feedback mechanism where the delay unit is calibrated using the actual PWM output and system clock. The calibration process measures the actual delay introduced by the delay unit and adjusts the delay parameters accordingly, compensating for variations due to process, voltage, and temperature. This feedback-based calibration ensures reliable and consistent step-size across different operating conditions.
3Measurement precision
If MEP technology is used for high-resolution PWM, then resolution can be improved, but periodic software calibration is required which increases complexity and user intervention
Solution Approach 1:
The system implements self-service through automatic calibration functionality that performs the calibration process without requiring user intervention. The calibration is integrated into the system operation, allowing the high-resolution PWM to be configured and calibrated automatically during initialization or operation, eliminating the need for periodic software calibration by the user.
4Measurement precision
If a single delay line is used for each PWM channel to achieve high precision, then the resolution is improved, but the chip area increases significantly
Solution Approach 1:
The system implements a shared delay line resource that can be used by multiple PWM channels. The delay line is time-multiplexed or otherwise shared among channels, allowing each channel to access the high-precision delay functionality without requiring dedicated delay lines. This universal resource approach significantly reduces the total chip area while maintaining high resolution for all channels.
Data Source
AI summary
In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.