Delay-Locked Loop Control for DRAM Read Phase Alignment
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Solution Overview
Problem
In dynamic random access memory (DRAM) systems, delay-locked loop (DLL) circuits face misalignment issues between input clock signals and output data due to response time delays, leading to inefficiencies in power consumption and performance during read operations.
Innovation Solution
A DLL circuit with a control unit that generates a control signal based on access start and end signals, utilizing a counter or timer to adjust the delay line between read operations, ensuring phase alignment and minimizing power consumption by activating the delay line only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DLL circuit is turned off between read operations to limit power consumption, then power consumption is reduced, but the voltage saturation causes misalignment between input clock signal and output data when the DLL is turned on again
Solution Approach 1:
The patent applies preliminary action by proactively adjusting the delay line before the DLL circuit is fully activated. The control unit detects when the DLL is turned on and preemptively modifies the delay amount to compensate for the upcoming voltage transition, ensuring phase alignment is maintained despite the power-saving shutdown cycle
Solution Approach 2:
The patent implements feedback by having the control unit continuously monitor the DLL circuit's operational state and dynamically adjust the delay line accordingly. When the DLL transitions from off to on state, the feedback mechanism triggers a compensatory delay adjustment to correct for voltage saturation effects and maintain proper phase alignment
2Speed
If the DLL circuit responds immediately to read requests, then response time is reduced, but the voltage saturation delay causes misalignment between clock and data signals
Solution Approach 1:
The control unit performs preliminary action by detecting the DLL activation state in advance and adjusting the delay line before the voltage saturation fully develops. This proactive adjustment ensures that when the DLL responds to read requests, the phase alignment is already corrected, maintaining both fast response and precise signal alignment
Solution Approach 2:
The patent applies preliminary anti-action by implementing a compensatory mechanism that counteracts the expected negative effect of voltage saturation before it occurs. The control unit anticipates the phase misalignment caused by rapid voltage changes and pre-applies an opposing delay adjustment to neutralize the harmful effect
Data Source
AI summary
A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.