Delay Locked Loop With Replica Delay Calibration for PVT Skew
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay locked loops face synchronization issues due to process voltage temperature (PVT) variations, leading to clock skew and offset between internal circuits and replica circuits, which prevents accurate synchronization with external clocks in electronic devices.
Innovation Solution
A delay locked loop design incorporating first, second, and third delay circuits, phase detectors, and controllers to detect and adjust delays, ensuring the third delay circuit replicates the second delay circuit's operation, thereby maintaining synchronization despite PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replica circuits are used to synchronize internal circuits with external clock, then clock skew compensation is achieved, but process voltage temperature (PVT) variations cause differences between internal and replica circuits leading to synchronization failure
Solution Approach 1:
The delay locked loop is segmented into multiple independent delay circuits (first delay circuit, second delay circuit, third delay circuit) that can be individually calibrated. Each delay circuit is controlled by separate control signals (first control signal, second control signal, third control signal), allowing granular adjustment to compensate for PVT variations in different parts of the circuit independently.
Solution Approach 2:
The invention dynamically adjusts delay parameters by varying control signals applied to each delay circuit based on detected phase differences. The first controller and second controller modify delay amounts in real-time by changing control parameters, enabling the system to adapt to PVT variations and maintain synchronization accuracy under different operating conditions.
2Measurement precision
If multiple delay circuits are added to compensate for PVT variations, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The invention uses a replica delay circuit (third delay circuit) that copies the structure and delay characteristics of the actual delay circuit (second delay circuit). By comparing the output of the replica circuit with the actual circuit through phase detectors, the system can detect and correct delays without requiring complete duplication of all circuit elements, reducing complexity while maintaining measurement precision.
Solution Approach 2:
The system implements feedback loops where phase detectors continuously monitor phase differences between clock signals, and controllers automatically adjust delay circuit parameters based on this feedback. This closed-loop control enables accurate phase detection and synchronization while minimizing the need for overly complex open-loop compensation circuits.
Data Source
AI summary
A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.