Delay-Locked Loop Sampling Circuit for Jitter and Offset Elimination
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Solution Overview
Problem
Analog delay locked loop (DLL) circuits face instability due to high operation frequency and require large low pass filters (LPFs) for noise suppression, leading to increased production cost and size.
Innovation Solution
The DLL circuit is redesigned to include a phase-frequency detector, a sampler, a charge pump, a bias generator, and a voltage-controlled element, which eliminates the need for an LPF by reducing operation frequency through sampling and XNOR gate operations, allowing stable operation without an LPF and reducing production costs and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operation frequency of the analog DLL circuit is high, then the clock synchronization speed is improved, but the control voltage changes too fast causing instability
Solution Approach 1:
The patent introduces a sampler that operates at a lower frequency than the input clock signal, converting the continuous high-frequency control voltage into periodic sampled values. This periodic sampling action allows the system to maintain high-speed clock synchronization while processing control signals at a stable, lower frequency, thus resolving the contradiction between speed and stability.
2Stability of the object's composition
If a large low pass filter is used to suppress high frequency noise, then the stability is improved, but the production cost and size increase
Solution Approach 1:
The patent extracts and removes the traditional large low pass filter from the DLL circuit by implementing a digital sampling-based control mechanism. The sampler and counter combination provides noise suppression and stability without requiring the large analog filtering components, thus achieving stability while reducing circuit size and production cost.
Solution Approach 2:
The patent replaces the analog low pass filter (mechanical/electrical filtering system) with a digital sampling and counting system. This substitution eliminates the need for large physical filtering components while maintaining or improving noise suppression performance, thereby reducing circuit size and complexity.
3Stability of the object's composition
If the operation frequency is reduced through sampling, then the stability is improved, but the clock synchronization speed may be affected
Solution Approach 1:
The patent segments the clock signal processing into two distinct paths: the input clock signal CKIN passes through the voltage-controlled delay line at its full high frequency to maintain synchronization speed, while the control voltage is separately sampled and processed at a lower frequency to ensure stability. This segmentation allows both high speed and stability to coexist without compromising either.
Data Source
AI summary
A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one difference signal by detecting a phase difference between an input clock signal and a feedback clock signal. The sampler outputs at least one sampled signal by delaying the difference signal in accordance with the input clock signal. The charge pump generates a control voltage in accordance with the sampled signal. The bias generator generates at least one bias voltage in accordance with the control voltage. The voltage-controlled element is controlled with the bias voltage to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.