Delay-Locked Loop Startup Using FLL to Prevent Sub-Harmonic Lock
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Solution Overview
Problem
Delay locked loops (DLLs) face issues with sub-harmonic locking during start-up, leading to incorrect delay values and potential stuck states, especially when reference clock frequencies are variable or unknown.
Innovation Solution
Implementing a frequency-locked-loop (FLL) mode to initially adjust the delay settings of the variable delay line to achieve frequency lock with the reference clock, followed by transitioning to a delay-locked-loop (DLL) mode, using a frequency monitor and oscillator feedback to ensure accurate phase lock without sub-harmonic locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a DLL uses a phase detector to achieve phase lock, then phase locking capability is improved, but sub-harmonic locking occurs leading to incorrect delay values
Solution Approach 1:
The locking process is segmented into two distinct phases: first achieving frequency lock using a frequency detector, then achieving phase lock using a phase detector. This segmentation prevents sub-harmonic locking by establishing frequency alignment before phase alignment begins.
Solution Approach 2:
Frequency locking is performed as a preliminary action before phase locking. The frequency detector and controller establish the correct operating frequency and eliminate sub-harmonic possibilities first, creating a stable foundation for the subsequent phase locking operation.
2Adaptability or versatility
If the DLL starts up with variable or unknown reference clock frequencies, then adaptability is improved, but sub-harmonic locking and stuck states increase
Solution Approach 1:
The system performs preliminary frequency detection and locking before attempting phase locking during start-up. This preliminary frequency alignment ensures that the DLL operates at the correct frequency regardless of whether the reference clock frequency is variable or unknown, preventing stuck states.
Solution Approach 2:
A frequency detector provides continuous feedback about the frequency relationship between the reference clock and the delay line output. This feedback enables the frequency controller to adjust the delay element settings to achieve and maintain correct frequency alignment, improving start-up reliability for variable frequencies.
3Measurement precision
If the DLL control loop increases or decreases delay to achieve phase lock, then phase locking capability is improved, but incorrect delay values are locked due to 360° phase error multiples
Solution Approach 1:
The delay control process is segmented into frequency control (using frequency detector) followed by phase control (using phase detector). This segmentation ensures that the delay value is first calibrated for correct frequency operation, eliminating the possibility of locking to incorrect delay values corresponding to 360° phase error multiples.
Solution Approach 2:
The frequency detector and frequency controller act as an intermediary between the reference clock and the phase detector. By establishing correct frequency alignment first, this intermediary ensures that when the phase detector subsequently operates, it does so at the correct operating point, preventing false locking to incorrect delay values.
Data Source
AI summary
This application relates to methods and apparatus for delay locked loops (DLLs). A DLL circuit includes a variable delay line, a phase detector and a delay controller. The DLL circuit is operable in a DLL mode in which a reference clock signal is input to the variable delay line and the delay controller controls a delay setting to achieve phase lock between the reference signal and an output signal. The DLL circuit is also operable in a frequency-locked-loop (FLL) mode, in which part of variable delay line is configured as a controlled oscillator to provide an oscillator signal, a frequency monitor determines a frequency relationship between the reference clock signal and the oscillator signal and the delay controller controls the delay setting to achieve frequency lock. The DLL circuit may configured to operate in the frequency-locked-loop mode on start-up and then transition to the DLL mode.