Independent DLL Training for Memory Channel Synchronization
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Solution Overview
Problem
Existing DDR memory systems face challenges in synchronizing data transfer across multiple channels due to variations in delay locked loops (DLLs), requiring complex master-slave DLL arrangements and strict design matching, which limits design flexibility and increases complexity.
Innovation Solution
A method and apparatus for training DLLs in a memory subsystem, where each channel includes a DLL that adjusts its delay to achieve a 180° phase difference with an input clock signal, allowing independent delay setting and eliminating the need for a master DLL, thereby enabling flexible and synchronized data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a master-slave DLL arrangement is used to synchronize data transfer across multiple channels, then synchronization reliability is improved, but device complexity increases due to the need for a master DLL and strict design matching
Solution Approach 1:
The patent removes the master DLL component from the system, extracting only the essential delay adjustment functionality from each slave DLL. Each channel's DLL operates independently without requiring a master controller, thereby reducing device complexity while maintaining synchronization through autonomous phase detection and adjustment mechanisms.
Solution Approach 2:
Each DLL is designed to automatically detect phase differences and adjust its own delay without external control from a master DLL. The self-service mechanism includes automatic phase detection circuits and feedback loops that enable each channel to independently maintain proper synchronization, eliminating the need for complex master-slave coordination.
2Measurement precision
If strict design matching is enforced for slave DLLs to achieve synchronized data transfer, then synchronization precision is improved, but ease of manufacture deteriorates due to increased manufacturing constraints
Solution Approach 1:
The patent employs parameter changes by allowing each DLL to dynamically adjust its delay parameter based on detected phase differences rather than requiring fixed, matched delay characteristics. This dynamic adjustment capability enables synchronization precision to be achieved through operational parameter tuning rather than strict manufacturing specifications.
Solution Approach 2:
The DLL design incorporates dynamic phase detection and adjustment mechanisms that adapt to variations in individual channel characteristics. Rather than relying on static, matched designs, the system dynamically compensates for differences between channels, making the manufacturing process more flexible while maintaining synchronization precision.
3Adaptability or versatility
If independent DLL configuration is allowed for each channel, then design flexibility is improved, but difficulty of detecting and measuring increases due to lack of centralized control
Solution Approach 1:
The patent segments the DLL control function into independent units for each channel, with each DLL containing its own phase detection and adjustment circuitry. This segmentation provides design flexibility while maintaining measurability, as each segment can be independently configured and tested without affecting other channels.
Solution Approach 2:
Each DLL incorporates feedback mechanisms that continuously monitor phase relationships and automatically adjust delay settings. This feedback approach simplifies detection and measurement by providing real-time information about synchronization status, eliminating the need for complex centralized measurement systems while maintaining independent channel configuration.
Data Source
AI summary
A method and apparatus for training a DLL in a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory coupled to convey data read therefrom on one or more channels. Each memory channel may include a delay locked loop (DLL) configured to apply a desired amount of delay to a data strobe signal received from the memory during a read operation. Upon detecting a read request, a controller may initiate a training procedure in which the DLL is trained to the desired delay. During the training procedure, an input clock signal may be provided to the DLL. The delay within the DLL may be adjusted until an output clock signal has a desired phase relationship with the input clock signal. Once the desired phase relationship is attained, the training procedure may be terminated and the DLL input may be switched to receive the data strobe signal.