Delay-Locked Loop Weight Storage for Stable Duty Ratio
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Solution Overview
Problem
Conventional delay locked loops (DLLs) in semiconductor memory devices malfunction under worst operating conditions such as noise interference, process/voltage/temperature (PVT) variations, and frequent power down mode entries/ exits, leading to incorrect data synchronization and system malfunctions due to changes in the duty ratio of the DLL clocks.
Innovation Solution
A DLL design that includes a delay-locking unit, phase detection unit, weight storage unit, and phase mixing unit, where the weight selection signal is stored during a predetermined period when the delay clocks are locked, allowing the DLL to maintain a stable duty ratio even under adverse conditions by applying a consistent weight to the delay clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional DLL is used to synchronize internal clock with external clock, then phase synchronization can be achieved, but the DLL malfunctions under worst operating conditions such as noise interference, PVT variations, and frequent power down mode transitions
Solution Approach 1:
The patent stores the weight selection signal in advance during a predetermined period when delay clocks are locked, before adverse operating conditions occur. This preliminary storage of the correct weight selection signal ensures that even when noise interference, PVT variations, or power down mode transitions occur, the DLL can restore and maintain the correct duty ratio by retrieving the previously stored weight selection signal, thereby preventing malfunction under worst operating conditions.
2Adaptability or versatility
If the phase detection unit continuously detects phase difference to maintain synchronization, then the DLL can adapt to phase changes, but the duty ratio of DLL clocks becomes unstable under adverse conditions
Solution Approach 1:
The patent introduces a weight storage unit as an intermediary between the phase detection unit and the phase mixing unit. The weight storage unit stores the weight selection signal determined by the phase detection unit during stable operating conditions. When adverse conditions occur, this stored weight selection signal acts as a mediator to maintain stable duty ratio in the phase mixing unit, preventing duty ratio instability while allowing the phase detection unit to continue adapting to phase changes.
3Device complexity
If the DLL operates without storing weight selection signal, then the device complexity is reduced, but the DLL cannot maintain stable duty ratio under worst operating conditions
Solution Approach 1:
The patent segments the DLL into distinct functional units: a delay-locking unit, a phase detection unit, a weight storage unit, and a phase mixing unit. By adding the weight storage unit as a separate segment, the patent enables duty ratio stability under adverse conditions without significantly increasing overall device complexity. The segmentation allows the stored weight selection signal to be independently managed and applied only when needed, maintaining simplicity while improving reliability.
Data Source
AI summary
A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit.