Double Layer Metal Power MOSFET Gate Pad Overlap
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Solution Overview
Problem
The large size of gate pads in discrete metal oxide semiconductor field effect transistor (MOSFET) devices limits the active area, as they occupy a significant portion of the die and often include inactive areas beneath them, restricting the functional channel for current conduction.
Innovation Solution
The implementation of overlapping first and second metal layers, with an intermetal dielectric for electrical isolation, allows for increased active area without expanding the device size, by reducing inactive areas and enabling the gate structure to overlay active source regions, thereby enhancing heat transfer and current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate pad is made large enough to accommodate bond wire or other attachment, then the bonding area is adequate, but the active area is limited because the gate pad takes up a large portion of the die
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-plane layout to a multi-layer vertical structure. The gate pad is positioned in a first metal layer while the source contact is in a second metal layer, allowing horizontal overlap that would be impossible in a single plane. This vertical stacking enables the gate pad to provide adequate bonding area while the source contact extends into the active area beneath it, effectively resolving the area conflict by utilizing the third dimension (depth).
2Area of stationary object
If the gate structure is sized to provide adequate bonding area, then the bonding requirement is met, but the inactive area increases which limits the active area
Solution Approach 1:
The invention resolves the inactive area problem by moving the source contact to a different vertical layer (second metal layer) where it can extend beneath the gate structure. This allows the source contact to occupy space that would traditionally be inactive, converting it into functional active area. The gate structure maintains its bonding area in the first metal layer while the source contact's vertical extension eliminates the need for lateral spacing, reducing inactive area by 25 µm or more.
3Reliability
If the source contact is isolated from the gate structure by a gap to maintain minimum distance, then proper isolation is provided, but the active area is reduced
Solution Approach 1:
The patent introduces an intermetal dielectric layer as an intermediary between the gate pad (first metal layer) and the source contact (second metal layer). This dielectric mediator provides the necessary electrical isolation and maintains proper spacing while allowing the two conductive elements to overlap horizontally. The intermetal dielectric enables close proximity and vertical stacking without direct contact, preserving isolation requirements while maximizing active area utilization.
4Reliability
If the edge of the source contact defines an inactive area below the gate bus, then isolation is maintained, but the active area is limited
Solution Approach 1:
The invention eliminates the inactive area constraint by relocating the source contact to a second metal layer where it can extend vertically beneath the gate bus structure. This vertical positioning allows the source contact to utilize the space underneath the gate bus that would traditionally be inactive, converting it into functional active area while maintaining proper isolation through the intermetal dielectric layer between the layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the active area by up to 5% or more, reduces inactive areas by 25 um or more, and improves the 'on' resistance of power transistors, such as drain-source resistance, without increasing the device size, allowing for more flexible gate pad placement and improved performance.
Implementation Method 1
an intermetal dielectric can provide electrical isolation between the portions of the first and second metal layers that overlap
Data Source
AI summary
This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.