Arithmetic Processor DMA Instruction Embedding
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Solution Overview
Problem
In systems performing large-scale arithmetic operations, efficiently updating instructions for DMA communication between PCIe boards is difficult, especially in architectures with multiple nodes, leading to inefficiencies in data processing and operation correspondence.
Innovation Solution
An arithmetic processor with a detection unit that identifies instructions to be executed after DMA completion within the DMA request instruction and a data processing unit that processes data transferred by DMA, allowing for updated correspondence and efficient operation in multi-stage node architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA is used for data transferring between lower nodes and upper node, then data transfer efficiency is improved, but it is difficult to change instructions to improve processing efficiency after DMA completion
Solution Approach 1:
The patent applies preliminary action by embedding the post-DMA processing instruction information within the DMA request instruction itself before the DMA transfer is initiated. This allows the processing instructions to be prepared and stored in advance, enabling the upper node to execute them immediately after DMA completion without waiting for separate instruction provisioning, thus resolving the inflexibility issue while maintaining high data transfer efficiency.
2Productivity
If correspondence between data and instructions is updated after DMA initiation, then processing efficiency is improved, but hardware changes are required
Solution Approach 1:
The patent uses copying by placing a copy of the processing instruction information directly into the DMA request instruction structure. This allows the upper node to have immediate access to the processing instructions without requiring complex hardware modifications or additional communication overhead. The instruction information is copied into the existing DMA request framework, enabling flexible updates without increasing hardware complexity.
3Productivity
If instructions are configured in multi-stage node architectures, then system performance is improved, but managing correspondence between nodes becomes complex
Solution Approach 1:
The patent applies merging by combining the data transfer request and the processing instruction information into a single unified DMA request instruction structure. This integration allows multi-stage node architectures to maintain efficient data transfer and processing while reducing the complexity of managing separate instruction channels. The merged structure simplifies correspondence management between nodes by eliminating the need to track separate instruction and data streams.
Data Source
AI summary
One aspect of the present disclosure relates to an arithmetic processor including a detection unit that detects instruction information, wherein an instruction including a processing instruction to be performed after completion of DMA (Direct Memory Access) in a DMA request instruction is described in the instruction information and a data processing unit that uses data transferred by the DMA request instruction to execute an operation corresponding to the processing instruction based on the instruction information detected by the detection unit.