DMA Control Circuitry for Array Broadcast and Reduction
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Solution Overview
Problem
Existing systems for performing array operations in memory circuitry, such as Seeded Graph Matching and Breadth First Search, are resource-intensive and burden the processor pipelines, especially for large graphs, due to the need for frequent memory access and atomic operations, leading to inefficiencies and load imbalances.
Innovation Solution
The introduction of direct memory access (DMA) control circuitry with enhanced instruction sets that enable autonomous data broadcast, array broadcast, and array reduction operations, allowing for efficient communication of data to multiple memory addresses and performing operations on data stored in memory locations without involving the processor pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional processor-based array operations are used, then data communication and atomic operations can be performed, but processor pipeline resources are burdened and traffic within the processor increases
Solution Approach 1:
The patent extracts array broadcast and reduction operations from the processor pipeline to dedicated DMA control circuitry. The DMA controller independently executes these operations using specialized instructions, removing the computational burden from the processor while maintaining the necessary data communication and atomic operation capabilities.
Solution Approach 2:
The patent introduces an intermediary DMA controller that mediates between memory and the processor for array operations. This intermediary handles data movement and atomic operations directly in memory, reducing processor involvement and pipeline traffic while enabling efficient array broadcast and reduction through specialized hardware support.
2Adaptability or versatility
If frequent memory access is performed for array operations, then data can be communicated to multiple vertices, but resource burdens increase and load imbalances occur
Solution Approach 1:
The patent implements preliminary action by having the DMA controller prepare and execute array broadcast operations before the processor needs the results. The controller independently manages memory access patterns for graph operations, pre-loading and pre-processing data to reduce subsequent resource consumption and eliminate load imbalances.
Solution Approach 2:
The patent enables self-service by allowing the DMA controller to autonomously perform array operations and memory access without continuous processor intervention. The controller manages its own operation queue and executes atomic operations directly in memory, reducing overall system resource consumption while maintaining versatile data communication for graph workloads.
Data Source
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AI summary
The present disclosure is directed to systems and methods of performing one or more broadcast or reduction operations using direct memory access (DMA) control circuitry. The DMA control circuitry executes a modified instruction set architecture (ISA) that facilitates the broadcast distribution of data to a plurality of destination addresses in system memory circuitry. The broadcast instruction may include broadcast of a single data value to each destination address. The broadcast instruction may include broadcast of a data array to each destination address. The DMA control circuitry may also execute a reduction instruction that facilitates the retrieval of data from a plurality of source addresses in system memory and performing one or more operations using the retrieved data. Since the DMA control circuitry, rather than the processor circuitry performs the broadcast and reduction operations, system speed and efficiency is beneficially enhanced.