Multi-Directional Data Padding During DMA Memory Reads
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Solution Overview
Problem
The existing data padding techniques in neural network convolution calculations are limited by the sequential operations of reading data and padding, which restricts processing speed and leads to inefficient use of hardware resources.
Innovation Solution
A data padding device and method that performs data padding in multiple directions simultaneously with reading, utilizing a DMA circuit and data processing circuit to generate padding data in both internal and external memory, enhancing data processing speed and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data padding is performed sequentially after reading data, then the padding operation can be completed accurately, but the data processing speed is limited
Solution Approach 1:
The patent applies preliminary action by performing data padding operations concurrently with the data reading process. The DMA circuit initiates padding operations before the reading process completes, using generated padding data to fill memory locations in advance. This allows the padding to be substantially completed before the reading process finishes, eliminating the sequential wait time and improving data processing speed while maintaining padding accuracy through controlled generation based on read data patterns.
2Device complexity
If data padding is performed only after reading data, then the reading process is simple, but hardware resources are wasted due to limited data usage
Solution Approach 1:
The patent implements continuity of useful action by having the DMA circuit continuously generate and store padding data during the entire reading process, rather than idle-waiting after reading completes. The circuit maximizes hardware resource utilization by keeping the padding generation logic actively producing useful padding data throughout the reading operation, ensuring that hardware resources are productively engaged and image data is fully utilized without waste.
3Productivity
If multi-directional padding is performed concurrently with reading, then data processing speed is enhanced, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing the DMA circuit with multi-functional capability to handle multiple padding directions (horizontal, vertical, and diagonal) using a unified circuit architecture. The circuit selectively activates different padding direction logic based on control signals, allowing one circuit structure to perform multiple padding functions. This reduces overall device complexity compared to having separate dedicated circuits for each padding direction, while still achieving enhanced data processing speed through concurrent multi-directional padding operations.
Data Source
AI summary
A data padding device includes an internal memory, a direct memory access (DMA) circuit and a data processing circuit. The DMA circuit performs, according to a first padding control signal, data padding in a first direction on raw data during a process of reading the raw data from an external memory to generate first-direction padding data, and stores the first-direction padding data to the internal memory, wherein the first-direction padding data includes the raw data and first padding data originated from the raw data. The data processing circuit performs, according to a second padding control signal, data padding in a second direction on the first-direction padding data during a process of reading the first-direction padding data from the internal memory to generate second-direction padding data, wherein the second-direction padding data includes the first-direction padding data and second padding data originated from the first-direction padding data.