Direct Memory Access Controller Burst Transmission
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Solution Overview
Problem
In VoIP phone systems, the frequent generation of interrupt signals by the direct memory access controller (DMAC) leads to a decrease in system performance due to the processor's frequent access to external memory, especially when using low-capacity output storage media.
Innovation Solution
A method and apparatus for controlling direct memory access that involves reading and storing data in response to a DMAC operation request, transmitting data in initial and reset burst sizes, and generating an interrupt signal only when all data are transmitted, thereby minimizing the frequency of interrupt signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DMAC generates interrupt signals frequently to transmit data in small units, then the data transmission is completed, but the system performance decreases due to frequent processor access to external memory
Solution Approach 1:
The patent segments the interrupt signal generation process by dividing data transmission into multiple burst phases (initial burst, middle burst, final burst) with different interrupt generation rules. The DMAC controller transmits data in segmented bursts while controlling interrupt signals to be generated only at specific completion points, thereby reducing the frequency of processor interventions while maintaining transmission progress.
Solution Approach 2:
The patent implements periodic action by establishing a structured transmission pattern with initial burst transmission followed by middle burst transmissions and final burst transmission. Each phase has predetermined conditions for interrupt generation, creating a periodic rhythm of data transmission and processor notification that optimizes system performance by avoiding continuous interrupt generation.
2Ease of manufacture
If a low-capacity output storage medium is used to reduce manufacturing costs and size, then the VoIP phone system becomes more compact and cheaper, but the DMAC must generate more interrupt signals
Solution Approach 1:
The patent applies dynamics by making the DMAC controller adapt its transmission and interrupt generation behavior based on the storage medium capacity. The controller dynamically adjusts burst sizes and interrupt generation timing according to the available storage space, optimizing the balance between using low-capacity media and minimizing interrupt frequency.
Solution Approach 2:
The patent changes parameters by modifying the burst size and interrupt generation conditions based on the output storage medium capacity. When low-capacity media is detected, the system adjusts transmission parameters to transmit data in optimized bursts with controlled interrupt generation, thereby reducing the harmful effect of frequent interrupts while maintaining compatibility with small storage media.
3Reliability
If the processor accesses external memory frequently to process interrupt signals, then the interrupt signals are handled, but the system performance steeply decreases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the DMAC controller with transmission parameters and burst size information before data transmission begins. The controller preliminarily determines the optimal transmission strategy based on storage capacity, thereby reducing the need for frequent processor interventions during actual transmission and improving overall system performance.
Data Source
AI summary
Provided are a method and apparatus for controlling direct memory access. In the method, data to be transmitted are read and stored in response to a direct memory access controller (DMAC) operation request, and a portion of the data corresponding to an initial burst size is first transmitted to a data destination. After resetting a burst size according to a state of the data destination, another portion of the data corresponding to the reset burst size is second-transmitted to the data destination. If all the data are not transmitted through the first-transmission and the second-transmission, the second-transmission is repeated until all the data are transmitted. If all the data are transmitted through the first-transmission and the second-transmission, an interrupt signal is generated. Therefore, interrupt signals can be less generated, and thus the processor can access an external memory less frequently, thereby increasing system performance.