DMLED Test Module Clock Domain Synchronization
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Solution Overview
Problem
Existing methods for testing integrated circuits, such as ATPG and BIST, face challenges in at-speed testing of systems with multiple clock domains, leading to unreliable test results due to synchronization issues between clock domains with different frequencies, and fail to cover all functional aspects of System-on-Chip (SoC) devices effectively.
Innovation Solution
The implementation of a Direct Memory Load Execute Dump (DMLED) test module that loads and executes test cases independently of the processor's clock, allowing for the synchronization of signals across clock domains, and dumps result signatures back to the tester, thereby enabling comprehensive testing at operational clock rates without interference from adjacent cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate embedded test circuitry is used to test individual circuit blocks, then test coverage of individual circuits is improved, but device complexity increases due to additional test input and output ports
Solution Approach 1:
The wrapper cell is designed to perform both functional operation and test mode operation through a single unified structure. The multiplexer within the wrapper cell allows it to switch between passing functional signals and test signals, eliminating the need for completely separate test circuitry while maintaining comprehensive test coverage.
Solution Approach 2:
The patent combines the functional interface and test interface into a single wrapper cell structure. The wrapper cell integrates the multiplexer, flip-flop, and control logic into one unit that handles both normal operation and test operation, reducing the overall device complexity compared to having separate embedded test circuitry for each core.
2Reliability
If ad hoc clock shaping techniques are used to synchronize signals across clock domains, then reliability of test results is improved, but device complexity increases
Solution Approach 1:
The wrapper cell acts as an intermediary between different clock domains. It captures signals at one clock domain using its flip-flop and then outputs them at another clock domain, effectively mediating the synchronization without requiring complex clock shaping circuitry. The clock domain crossing is handled through the sequential nature of the flip-flop rather than ad hoc synchronization techniques.
Solution Approach 2:
The patent extracts the clock domain synchronization function from the signal path and embeds it within the wrapper cell structure. By capturing signals in the flip-flop and outputting them at the target clock domain, the synchronization function is taken out of the complex ad hoc clock shaping domain and integrated into a simpler, more reliable wrapper cell implementation.
3Adaptability or versatility
If wrapper cells with multiplexers are used to switch between functional mode and test mode, then adaptability is improved, but device complexity increases
Solution Approach 1:
The wrapper cell is designed as a universal interface that handles both functional operation and test operation through a single structure. The multiplexer enables the wrapper cell to adapt its behavior based on the operational mode, providing versatility while maintaining a compact implementation that does not significantly increase device complexity.
Data Source
AI summary
A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case into a memory using the DMLED test module, loading initialization signatures of fixed pattern into the memory using the DMLED test module, and executing the test case at an operating clock rate of a processor. The method further includes writing result signatures into the memory, and dumping the results signatures from the memory to a tester using the DMLED test module.