DMOS Transistor Drift Region Doping for Low On-Resistance
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Solution Overview
Problem
Existing high withstand voltage MOS transistors achieve high source-drain breakdown voltage but struggle with low on resistance and limited current driving capacity, leading to breakdown issues due to electric field concentration.
Innovation Solution
The semiconductor device incorporates a second conductivity type body layer with a channel region, a source layer, a gate electrode, a first well layer for voltage boosting, a second well layer for reduced on resistance, and a third well layer in the drift region, along with specific doping and thermal processing to optimize the structure and reduce on resistance while maintaining high voltage strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a high withstand voltage MOS transistor structure is used to achieve high source-drain breakdown voltage, then the breakdown voltage is improved, but the on resistance increases and current driving capacity decreases
Solution Approach 1:
The patent applies local quality by creating different doping concentration regions within the drift region. Specifically, a first doping concentration region with higher concentration and a second doping concentration region with lower concentration are formed at different depths, allowing the structure to simultaneously achieve low on-resistance near the surface and high breakdown voltage at deeper regions.
Solution Approach 2:
The patent changes the doping concentration parameter throughout the drift region depth. By forming multiple regions with different doping concentrations (higher concentration near the surface, lower concentration at deeper regions), the patent optimizes both the on-resistance and breakdown voltage characteristics, resolving the contradiction between these two parameters.
2Strength
If the drift region is optimized for high voltage withstand capability, then the breakdown voltage is improved, but the electric field concentration causes breakdown issues and current driving capacity is limited
Solution Approach 1:
The patent addresses electric field concentration by creating localized doping regions with different concentrations. The higher doping concentration region is positioned to handle high electric field areas, while the lower doping concentration region maintains the depletion layer for voltage blocking, thereby distributing the electric field more evenly and preventing concentration-induced breakdown.
Solution Approach 2:
The patent performs preliminary doping action during manufacturing to pre-establish the optimal doping concentration profile in the drift region before the device operates. This preliminary structuring of the drift region with graded doping concentrations prevents electric field concentration issues from arising during high-voltage operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a MOS transistor with improved current driving capacity and lower on resistance, maintaining high source-drain breakdown voltage while preventing breakdown due to electric field concentration, enhancing overall performance.
Implementation Method 1
The drain electric field is eased by the expansion of the depletion layer in the drift region 109
Implementation Method 2
An N+ type N well layer 107 (N+W) is formed on the surface of the epitaxial layer 101, and an N+ type drain layer 108 (NSD) on the surface of N well layer 107
Data Source
AI summary
This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is disposed beneath the gate electrode and away from the N well layer with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode of the drain layer side. Also, the N well layer is formed on the surface of an epitaxial layer in the region that includes a P+L layer. The edge of the N well layer of the drain layer side is located near the edge of the P+L layer of the drain layer side and away from the N well layer. This space makes the expansion of depletion layer from the P+L layer easier, further improving the withstand voltage.