DMOS Superlattice Drift Region With Field Plate Depletion
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Solution Overview
Problem
Current semiconductor devices face limitations in achieving enhanced charge carrier mobility and performance due to issues like alloy scattering and sub-stoichiometric insulating properties at interfaces, which affect device efficiency and reliability.
Innovation Solution
The implementation of a semiconductor superlattice structure with stacked groups of semiconductor and non-semiconductor monolayers, where the non-semiconductor monolayers are constrained within the crystal lattice of adjacent semiconductor portions, reduces effective mass and scattering, improving charge carrier mobility and providing enhanced insulating properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional semiconductor structure is used, then the device structure is simple, but the charge carrier mobility is insufficient
Solution Approach 1:
The patent applies composite materials by creating a superlattice structure consisting of alternating semiconductor and non-semiconductor monolayers. This composite structure enhances charge carrier mobility through reduced scattering effects while maintaining a manageable device architecture. The superlattice integrates multiple material types (semiconductor and non-semiconductor) in a periodic arrangement to achieve improved electrical properties without excessive structural complexity.
Solution Approach 2:
The patent segments the drift region into a superlattice structure with alternating monolayers of semiconductor and non-semiconductor materials. This segmentation creates multiple interfaces that reduce scattering effects on charge carriers, thereby improving mobility. The drift region is divided into repeating units of different material types, allowing enhanced charge transport through the segmented architecture.
2Productivity
If uniform doping is used, then the manufacturing process is simple, but the device performance and efficiency are limited
Solution Approach 1:
The patent applies local quality by implementing a non-uniform doping profile within the drift region of the superlattice structure. Different regions of the drift region receive different doping concentrations, allowing optimization of device performance characteristics such as breakdown voltage and on-resistance. The doping profile is tailored locally to match the specific functional requirements of different portions of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to increased charge carrier mobility, reduced scattering, and improved device performance by confining carriers effectively and acting as a barrier to dopant diffusion, while also enabling piezoelectric and ferroelectric properties for various applications.
Implementation Method 1
The superlattice structure improves charge carrier mobility by reducing scattering effects
Implementation Method 2
forming field plate layer adjacent the drift region and configured to deplete the drift region
Data Source
AI summary
A method for making a double-diffused MOS (DMOS) device may include forming a semiconductor layer having a first conductivity type, forming a drift region of a second conductivity type in the semiconductor substrate, forming spaced-apart source and drain regions in the semiconductor layer, and forming a first superlattice on the semiconductor layer. The first superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate above the first superlattice, and a forming field plate layer adjacent the drift region and configured to deplete the drift region.