Deep Neural Network Parallelism Factor Determination on FPGA
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Solution Overview
Problem
Deep neural networks (DNNs) face challenges in efficient implementation on field-programmable gate arrays (FPGAs due to limited resources such as memory, processing elements, and bandwidth, which hinders performance enhancement.
Innovation Solution
A method is introduced to determine a parallelism factor for processing operations in FPGAs based on the workload and configuration of each layer in a DNN, allowing for optimized allocation of resources through channel and kernel parallelization factors, ensuring efficient use of available resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FPGAs are used to implement DNN due to inherent pipeline feature and better performance, then processing speed and performance are improved, but resource limitations (memory, processing elements, bandwidth) worsen
Solution Approach 1:
The patent segments the DNN computation into multiple layers and further divides each layer's operations into parallel processing tasks. By determining a parallelism factor for each layer, the system partitions the workload across available processing elements in the FPGA, enabling simultaneous execution of multiple operations while respecting resource constraints.
Solution Approach 2:
The patent introduces the dimension of parallelism by determining a parallelism factor that enables processing operations to be executed simultaneously across multiple processing elements. This transforms sequential layer processing into parallel execution, effectively utilizing the FPGA's inherent parallel architecture to overcome resource limitations.
2Productivity
If more processing elements are allocated to increase parallelism, then processing performance is improved, but resource consumption increases
Solution Approach 1:
The patent dynamically determines the parallelism factor for each layer based on the specific workload characteristics and available FPGA configuration. This allows the system to adaptively allocate processing elements to each layer, optimizing performance for different computational tasks while ensuring efficient utilization of the limited processing resources available in the FPGA.
Data Source
AI summary
The present disclosure relates to methods, systems, and computer program products for implementing a deep neural network in a field-programmable gate array (FPGA). In response to receiving a network model describing a deep neural network, a plurality of layers associated with the deep neural network may be determined. With respect to a layer in the plurality of layers, a parallelism factor for processing operations associated with the layer simultaneously by processing elements in an FPGA may be determined based on a workload associated with the layer and a configuration of the FPGA.