Neural Architectures TRIZ Cases

A system generates metadata encoding numerical characteristics of training data to verify input conformance.

A structural description framework simulates desired neuronal activity in neurosynaptic core circuits.

A method partitions neural network models into sub-models and deploys them on specific accelerators to optimize execution.

A unified training mechanism updates performance metric masks to select candidate neural network architectures meeting accuracy and latency requirements.

Cloud server generates optimal streak detection parameters to resolve calculation time bottlenecks during real-time document scanning.

A deep learning optimization framework manages heterogeneous distributed resources through dynamic task scheduling and neural network training.

A computation-oriented intermediate representation constructs physical graphs to optimize memory usage in neural network models.

A word embedding model processes concatenated text sequences to identify semantically similar concepts.

Segmented dynamical nodes fit neuroimaging data to resolve model complexity and improve measurement precision.

Segmenting weight precision levels with selective run-length encoding reduces memory size by up to 79% while maintaining recognition accuracy.

A rectifier linear unit predicts negative dot product outputs using intermediate magnitude thresholds to terminate computation early.

Conditional variational encoder reduces input dimensionality to train separate success and failure predictors for adversarial sampling.

A local keyword engine allocates dynamic memory blocks to process audio signals using neural networks.

Inverted spike-timing dependent plasticity adjusts synaptic weights to stabilize spiking neural network operation.

Consolidating activation data into local memory bins accelerates DNN throughput while lowering power consumption compared to traditional GPU architectures.

Reorders neural network execution to stream weight values sequentially, lowering power consumption and bandwidth usage in resource-constrained devices.

Mask layers identify and remove redundant neural network nodes, reducing memory storage without the processing overhead of sparse matrix operations.

Cross-bar synapse arrays enable on-chip training in neuromorphic systems, reducing power consumption and circuit area by removing Op-Amp, ADC, and DAC circuits.

Direct time and space connections enable machine learning models to capture long-term dependencies without vanishing gradients.

Transition table networks encode neural signals as alphanumeric strings to enable compact data processing.

A machine learning model update method applies a transformation function to remove erroneous data influence from trained parameters.

A calculation scheme decision system selects optimal processing methods for each neural network layer to reduce resource usage.

A training method applies potential functions to overparameterized model weights to enforce structural constraints during optimization.

Segmenting convolutional layers across multiple GPUs overcomes single-device memory limits while accelerating model updates.

Segmenting non-convex optimization with ADMM resolves vanishing gradient bottlenecks in stacked auto encoder regression training.

Segmenting 2-D convolutions into sequential 1-D passes reduces computational complexity while maintaining feature extraction precision.

Post-synaptic neurons use comparators to classify quasi-trained synapses and trigger reset signals.

A trained neural network classifies input data to select the optimum processing algorithm for computer vision systems.

Linearization subsystem converts convolution operations to matrix multiplication, reducing memory usage and energy consumption.

Nested local memory and preliminary data caching resolve FPGA resource constraints while sustaining high computation throughput.

Regularizing a style vector within an autoencoder latent space produces stable label vectors for machine learning classification tasks.

Trainable weights across transmitter, relay, and receiver algorithms optimize communication performance through unified end-to-end learning.

Calculates layer-specific parallelism factors based on workload and FPGA configuration to maximize resource utilization and reduce latency.

Segmenting spike processing into distinct input and output intervals prevents sequential delays, increasing data throughput in spiking neural networks.

Parallel dual arithmetic modules reduce memory bandwidth bottlenecks by dividing multi-channel image data processing across independent hardware units.

Segmenting a neural network into parameter and hyper-parameter parts via bi-level optimization retains accuracy on previous tasks while adapting to new ones.

An LSTM model identifies sensor drift by analyzing prediction errors against autocorrelation thresholds derived from historical process data.

A robustness indicator unit propagates input data through a dual artificial neural network to determine activation bounds.

A multilayer neural network controller updates its weight matrix using a case-divided loss function with penalty terms to maintain closed-loop stability.

A neuromorphic system uses lateral inhibition circuits to suppress post-neuron spikes across output lines for precise synaptic learning.

A sparse coding layer reconstructs normalized signals using dictionary atoms to enhance neural network classification accuracy.

Intermittent digital modules correct analog weight errors, balancing speed and accuracy in production.

A convolution operation device segments processing into multiple units and uses a buffer to retrieve new data for parallel execution.

An iterative training procedure selects small data samples to build classification models efficiently.

Reorganization circuits splice scattered output feature data subsets from parallel processing arrays into unified subsets, improving bus bandwidth utilization.

Multi-level partitioning minimizes wire length by placing frequently communicating cores on the same chip, reducing power consumption by 30-83%.

Segments connection weights into scaled and unscaled components to overcome hardware storage precision limits while maintaining learning accuracy.

DNN Surgery reduces parameter density in deep neural networks by pruning less important weights while maintaining accuracy through iterative retraining.

Coordinate embeddings update node positions based on relative distances, reducing data augmentation efforts while maintaining computational efficiency.

A system extracts attack vector sequences and generates signatures to predict subsequent cyber-attacks within a network.