Neurosynaptic Core Placement for Power Minimization
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Solution Overview
Problem
Power consumption and heat dissipation are significant barriers in exascale computing, particularly in neurosynaptic networks, where communication between cores consumes high energy due to wire length and inter-chip communication costs are much higher than on-chip communication.
Innovation Solution
The method involves modeling power consumption as wire length and using a multi-level partitioning algorithm to optimize the physical placement of neurosynaptic cores, minimizing total edge lengths and reducing power consumption by placing frequently communicating cores within the same chip, while also addressing fault-tolerant scenarios such as faulty grid locations and routers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If neurosynaptic cores are placed using default sequential placement, then the placement process is simple, but power consumption is high due to long wire lengths
Solution Approach 1:
The patent transforms the power minimization problem into a wire length minimization problem by changing the parameter representation. Power consumption is modeled as proportional to wire length, allowing the use of established wire length minimization algorithms to solve the power optimization problem. This parameter transformation enables the application of multi-level partitioning algorithms to achieve 30-83% power savings while managing computational complexity.
2Use of energy by moving object
If cores with frequent communication are placed on the same chip, then communication power is reduced, but chip area utilization becomes more complex
Solution Approach 1:
The patent applies multi-level partitioning to divide the neurosynaptic network into hierarchical groups. At the first level, cores are partitioned into clusters based on communication frequency. At subsequent levels, these clusters are further divided and assigned to different chips. This segmentation approach ensures that frequently communicating cores are placed on the same chip while distributing less connected cores across multiple chips, optimizing both communication power and area utilization.
Solution Approach 2:
The patent extends the placement problem from a two-dimensional chip layout to a multi-dimensional solution space that includes chip-to-chip spatial relationships. By modeling the system as a hierarchy of placement levels (intra-chip and inter-chip), the algorithm can optimize core placement across multiple spatial dimensions, reducing communication power for frequently interacting cores while properly utilizing available chip area.
3Loss of energy
If wire length is minimized to reduce power, then power consumption decreases, but the placement algorithm becomes more complex
Solution Approach 1:
The patent performs preliminary partitioning of the neurosynaptic network into clusters based on communication patterns before executing the detailed placement algorithm. This preliminary action identifies groups of cores that should be placed close together, reducing the search space for the subsequent wire length minimization phase. By pre-grouping cores with frequent communication, the algorithm achieves better energy efficiency without requiring excessively complex optimization procedures.
Data Source
AI summary
Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.