On-Chip Training Neuromorphic Architecture Using Cross-Bar Synapse Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing neuromorphic systems face challenges with high power consumption and large area requirements, making them inefficient as the size of the neural network increases, particularly in performing on-chip training with forward propagation, backward propagation, and weighted value update phases.
Innovation Solution
A neuromorphic system is designed with synapse arrays and neuron layers that utilize gated Schottky diodes or nonvolatile memory devices with charge storage layers, enabling on-chip training by performing all phases using hardware, minimizing memory and power consumption through cross-bar shaped synapse devices and efficient switching elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional neuromorphic systems use Op-Amp, ADC, and DAC circuits to perform on-chip training, then the system can perform forward propagation, backward propagation, and weighted value update operations, but the power consumption and area requirements increase significantly
Solution Approach 1:
The patent extracts and removes the power-intensive Op-Amp, ADC, and DAC circuits from the neuromorphic system. Instead, it uses simple cross-bar switch arrays where synapse weights are stored as conductance values in memory devices, and neuron activations are computed through passive Ohmic conduction during matrix-vector multiplications. This extraction of unnecessary components directly reduces power consumption while maintaining on-chip training capability through alternative hardware mechanisms.
Solution Approach 2:
The patent replaces the mechanical/electronic amplification and conversion mechanisms (Op-Amp, ADC, DAC) with direct physical conduction through cross-bar switches. The system uses Ohmic conduction in the cross-bar array to perform matrix-vector multiplications naturally, substituting complex electronic processing with simpler physical laws-based operations that consume less power.
2Adaptability or versatility
If conventional neuromorphic systems use Op-Amp, ADC, and DAC circuits to perform on-chip training, then the system can perform forward propagation, backward propagation, and weighted value update operations, but the circuit area increases
Solution Approach 1:
The patent extracts and removes the area-intensive Op-Amp, ADC, and DAC circuits from the neuromorphic system. Instead, it uses simple cross-bar switch arrays where synapse weights are stored as conductance values in memory devices, and neuron activations are computed through passive Ohmic conduction during matrix-vector multiplications. This extraction of unnecessary components directly reduces circuit area while maintaining on-chip training capability through alternative hardware mechanisms.
Solution Approach 2:
The cross-bar switch array serves multiple functions: it stores synapse weights as conductance values, performs matrix-vector multiplications during forward propagation, enables backward propagation through the same structure, and supports in-situ weight updates. This multi-functionality eliminates the need for separate dedicated circuits for each operation, significantly reducing the overall circuit area required for on-chip training.
3Productivity
If von Neumann-based structure is used to perform artificial intelligence operations, then the system can perform computations, but power consumption increases due to serial communication between memory and processor
Solution Approach 1:
The patent merges the storage and computation functions into a single integrated structure. The cross-bar switch array simultaneously stores synapse weights as conductance values and performs computations through passive Ohmic conduction during matrix-vector multiplications. This merging eliminates the separate memory and processor units required by von Neumann architecture, removing the need for data transfer between them and significantly reducing power consumption.
Solution Approach 2:
The patent replaces the active electronic data transfer mechanism between memory and processor with passive Ohmic conduction through the cross-bar array. The computation emerges naturally from the physical conduction of currents through the conductance-based weight storage, substituting active data movement with passive physical laws-based computation that consumes minimal power.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption and area usage, enabling efficient on-chip training by optimizing weight updates and error calculations within the neural network, improving performance and reducing memory requirements.
Implementation Method 1
synapse devices having a preset conductance are arranged in a cross-bar shape... conductances of the synapse devices represent weighted values of the neural network
Implementation Method 2
synapse devices having a preset conductance are arranged in a cross-bar shape... utilizing gated Schottky diodes or nonvolatile memory devices with charge storage layers
Data Source
AI summary
A neuromorphic system enabling on-chip training includes: synapse arrays where synapse devices are arranged in a cross-bar shape; a final neuron layer including a forward neuron and a backward neuron and connected to an output terminal of a last synapse array; neuron layers including a forward neuron, a backward neuron, and a memory storing signals used during a weighted value update operation of a neural network and arranged between the remaining synapse arrays except for a first and last synapse arrays; and an error calculation circuit detecting and outputting an error value of a target signal and an output signal of the forward neuron of the final neuron layer. Conductances of the synapse devices represent weighted values of the neural network and are changed by the weighted value update operation. Each synapse device is configured with a flash device, and the neuron layers are implemented with ultra-miniature devices.