Neuromorphic System With Lateral Inhibition For Spike Timing Dependent Plasticity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current neuromorphic systems for spike timing dependent plasticity (STDP) operations in spiking neural networks (SNNs) face challenges in enhancing synaptic learning selectivity and efficiency, particularly in the implementation of STDP algorithms for synaptic weight learning in neuromorphic array structures.
Innovation Solution
A neuromorphic system is designed with presynaptic neurons, signal generators, drivers, synapse units, and STDP control blocks, including memristors or memtransistors, and lateral inhibition circuits to improve synaptic learning selectivity by controlling spike timing and inhibiting post-neuron spikes across the array, enhancing the STDP operation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional STDP operations are implemented in neuromorphic systems, then synaptic learning can be performed, but synaptic learning selectivity is insufficient
Solution Approach 1:
The system divides the STDP operation into separate functional blocks: presynaptic neuron circuits, synapse units with memristors, and postsynaptic neuron circuits with STDP control blocks. Each block performs a specific function, allowing independent optimization and improving synaptic learning selectivity without requiring complete system redesign.
Solution Approach 2:
The patent introduces signal generator circuits as intermediaries that transform presynaptic and postsynaptic spikes into signals suitable for synaptic learning operations. These intermediary circuits enable precise control of spike timing differences and improve the selectivity of synaptic learning without directly modifying the core neuron circuits.
2Productivity
If STDP algorithm is implemented for synaptic weight learning, then neural network learning capability is achieved, but learning efficiency and performance are limited
Solution Approach 1:
The system performs preliminary transformation of presynaptic and postsynaptic spikes into learning signals before the actual STDP operation. Signal generators pre-process the spike signals to extract timing information and generate appropriate control signals for synapse units, reducing the time required during the actual learning operation.
Solution Approach 2:
The patent replaces traditional electronic timing control mechanisms with membrane capacitor-based timing mechanisms. The membrane capacitor naturally integrates incoming signals and generates spikes based on voltage thresholds, providing automatic timing control without requiring complex external timing circuits, thus improving learning efficiency.
3Reliability
If spike timing difference is used to determine learning degree, then biological plausibility is achieved, but precise timing control is difficult
Solution Approach 1:
The membrane capacitor in the postsynaptic neuron circuit automatically performs timing integration of incoming presynaptic signals. The capacitor's natural charging and discharging characteristics provide intrinsic timing control, eliminating the need for external timing control circuits and maintaining biological plausibility while simplifying operation.
Solution Approach 2:
The system changes the timing control parameter from external voltage control to membrane potential integration. By using the membrane capacitor's voltage integration property, the system naturally captures spike timing differences through parameter accumulation, making precise timing control more achievable while maintaining biological realism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively stabilizes synaptic learning in SNNs by improving synaptic learning selectivity and enhancing the performance of the STDP algorithm, allowing for more precise weight adjustments and efficient information transmission between neurons.
Implementation Method 1
Each of the synapse units may include a memristor or a memtransistor connected between an input line connected to an output terminal of the first driver and an output line
Implementation Method 2
a membrane capacitor configured to be charged with a membrane potential by the pre-neuron signal transmitted through the first transmission gate
Data Source
AI summary
Provided is a neuromorphic system for synaptic learning in a spiking neural network (SNN)-based neuromorphic array structure. Control blocks including a post-synaptic neuron, which generates a post-neuron spike, are disposed on output lines of a synapse array to implement a spike timing dependent plasticity (STDP) operation such that synaptic learning can be stably implemented in an SNN neuromorphic array. Also, a lateral inhibition circuit may be added. When a post-neuron spike is generated by an STDP control block connected to any one output line, the lateral inhibition circuit inhibits STDP control blocks connected to other output lines from generating spikes. Accordingly, learning selectivity can be improved, and thus the performance of an STDP algorithm can be improved.