Reconfigurable Doherty Transceiver Interface for Low-Noise Phased Arrays
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Solution Overview
Problem
Existing phased array antenna systems for millimeter-wave communication struggle to efficiently provide multiple power levels while maintaining good receive noise figure performance, and they often require significant area on integrated circuits due to the need for splitter and combiner circuitry.
Innovation Solution
A reconfigurable Doherty output network is introduced, which efficiently couples a Doherty power amplifier chain and a low noise amplifier (LNA) to an antenna port, reducing capacitance presented to the LNA and minimizing area consumption on integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional phased array antenna systems use splitter and combiner circuitry to provide multiple power levels, then power amplification capability is improved, but device area and complexity increase significantly
Solution Approach 1:
The patent combines the splitter and combiner functions into a single reconfigurable output network that performs both signal separation and combination operations. This merging of functions eliminates the need for separate splitter and combiner circuitry, thereby reducing the integrated circuit area while maintaining the capability to provide multiple power levels through the Doherty amplifier architecture.
Solution Approach 2:
The reconfigurable output network is designed to perform multiple functions: it acts as a splitter during transmit operations to separate signals for the main and auxiliary amplifier paths, and as a combiner to merge the amplified signals. This multi-functionality allows a single circuit element to replace what would traditionally require separate dedicated splitter and combiner components, reducing overall device area.
2Power
If traditional phased array systems include separate splitter and combiner circuitry, then power amplification is achieved, but device complexity increases
Solution Approach 1:
The patent merges the splitter and combiner into a single reconfigurable output network, reducing the number of discrete components and interconnections required. This consolidation simplifies the overall circuit architecture while maintaining the Doherty amplifier's ability to provide efficient power amplification across multiple power levels.
Solution Approach 2:
The reconfigurable output network employs dynamic switching mechanisms that allow the circuit to reconfigure its topology based on operational requirements. This dynamic capability enables the same circuit structure to perform both splitting and combining functions, reducing the need for multiple static circuit configurations and thereby simplifying the overall device complexity.
3Reliability
If capacitance is reduced at the LNA input, then receive noise figure performance is improved, but coupling efficiency may be affected
Solution Approach 1:
The patent modifies the capacitance parameter at the LNA input by optimizing the configuration of the reconfigurable output network. By adjusting the capacitive coupling and using switched capacitor networks, the design achieves lower input capacitance that improves noise figure performance while maintaining adequate signal coupling efficiency through proper impedance matching and coupling network design.
Solution Approach 2:
The reconfigurable output network acts as an intermediary between the amplifier paths and the LNA, providing impedance transformation and coupling optimization. This intermediary circuitry enables the system to achieve low input capacitance for improved noise performance while maintaining efficient signal transfer through its matching and coupling functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reconfigurable Doherty output network achieves efficient power amplification with improved power added efficiency (PAE) at backoff power levels, while reducing the overall chip area and cost, and maintaining good receive noise figure performance.
Implementation Method 1
a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil
Data Source
AI summary
A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.