Doherty PA Package Layout With Isolation Gaps and Asymmetric Die Areas
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Solution Overview
Problem
Current Doherty power amplifier packages face limitations in design flexibility and performance characteristics, particularly in asymmetric layouts where the peaking transistor die area is not optimally utilized, leading to suboptimal gain, linearity, and power-added efficiency.
Innovation Solution
A design-flexible power amplifier package platform that allows for various Doherty PA configurations by enabling multiple lead arrays with grouped leads and isolation gaps, allowing for asymmetrical die bond area allocation favoring peaking transistors, and incorporating impedance matching networks and phase delay elements to enhance signal amplification paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If symmetric two-way Doherty architecture is used, then manufacturing simplicity is maintained, but design flexibility and performance optimization are limited
Solution Approach 1:
The patent applies universality by creating a common package platform that can accommodate multiple Doherty PA configurations (two-way, three-way, four-way; symmetric and asymmetric). The standardized leadframe structure, die bond regions, and lead arrangements serve multiple functions across different amplifier configurations, enabling design flexibility without requiring entirely new package designs for each configuration.
Solution Approach 2:
The patent applies segmentation by dividing the package into modular components: standardized leadframe structure, configurable die bond regions, and separable signal paths. This modular approach allows different numbers and arrangements of carrier and peaking transistor dies to be integrated into the same platform, resolving the contradiction between design flexibility and manufacturing complexity.
2Reliability
If asymmetric die bond area allocation favoring peaking transistors is implemented, then gain and power-added efficiency are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by providing different die bond area sizes within the same package platform - larger die bond regions for peaking transistor dies and smaller regions for carrier transistor dies. This localized differentiation optimizes performance characteristics (gain, linearity, efficiency) while the overall standardized platform structure maintains ease of manufacture through repeatable fabrication processes.
3Power
If larger peaking transistor die size is used, then power-added efficiency and gain are enhanced, but die bond area requirements increase
Solution Approach 1:
The patent applies asymmetry by deliberately designing unequal die bond area allocations within the package - larger areas for peaking transistor dies to accommodate larger transistor sizes for enhanced power-added efficiency and gain, and smaller areas for carrier transistor dies. This asymmetric layout optimizes performance while the standardized overall package dimensions control the total area footprint.
4Adaptability or versatility
If multiple signal amplification paths are integrated, then functionality is enhanced, but cross-coupling between paths increases
Solution Approach 1:
The patent applies the intermediary principle by using isolation gaps and isolation structures (such as ground planes or shielding elements) positioned between adjacent carrier and peaking signal amplification paths. These intermediary elements act as barriers that reduce electromagnetic coupling and interference between the multiple signal paths, enabling enhanced functionality while minimizing harmful cross-coupling effects.
Data Source
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AI summary
Embodiments of Doherty Power Amplifier (PA) and other PA packages are provided, as are systems including PA packages. In embodiments, the PA package includes a package body (112) having a longitudinal axis (114), a first group of input-side leads (132-1, 134-1, 136-1) projecting from a first side (115) of the package body (112) and having an intra-group lead spacing, and a first group of output-side leads (132-2, 134-2, 136-2) projecting from a second side (117) of the package body (112) and also having the intra-group lead spacing. A first carrier input lead (130-1) projects from the first package body (112) side and is spaced from the first group of input-side leads (132-1, 134-1, 136-1) by an input-side isolation gap (137-1), which has a width exceeding the intra-group lead spacing. Similarly, a first carrier output lead (130-2) projects from the second package body (112) side, is laterally aligned with the first carrier input lead (130-1), and is separated from the first group of output-side leads (132-2, 134-2, 136-2) by an output-side isolation gap (137-2).