Domain Adaptive Processor for Wireless Standards
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Solution Overview
Problem
Wireless communication workloads require flexibility to accommodate new standards, but traditional systolic-array architectures trade off efficiency for limited flexibility, making them less adaptable to changing computational demands.
Innovation Solution
A domain adaptive processor with a configurable systolic-array fabric that includes management units, processing elements with multiple ports, registers, instruction memory, and a loop control unit, allowing for efficient execution of various wireless communication kernels with near-ASIC energy efficiency by minimizing control overhead and enabling on-the-fly kernel swapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional systolic-array architectures are used, then energy efficiency is improved, but flexibility deteriorates
Solution Approach 1:
The patent implements a dynamically reconfigurable systolic-array architecture where processing elements can change their operational mode and dataflow patterns on-the-fly. The configurable interconnect network allows dynamic routing of data between processing elements, enabling the same hardware to adapt to different wireless communication standards and computational kernels without sacrificing energy efficiency.
Solution Approach 2:
The processing elements are designed with multiple functional units that can be configured to perform different operations (e.g., multiplication, accumulation, logical operations). The same processing element can serve multiple functions by reconfiguring its internal logic and dataflow, eliminating the need for dedicated hardware for each function while maintaining high energy efficiency.
2Adaptability or versatility
If general purpose processors are used, then flexibility is improved, but energy efficiency deteriorates
Solution Approach 1:
The processor is segmented into multiple processing elements arranged in a systolic-array fabric, where each element is a simplified version of a general-purpose processor core. This segmentation allows parallel execution of multiple computational tasks while using less energy per operation compared to a single general-purpose processor, achieving both flexibility and energy efficiency.
Solution Approach 2:
The patent replaces the complex control mechanisms of general-purpose processors with a streamlined control architecture that uses pre-configured dataflow patterns and microcode. This substitution reduces the overhead of instruction decoding and control logic, lowering energy consumption while maintaining the ability to execute various wireless communication algorithms.
3Adaptability or versatility
If reconfiguration is enabled for different wireless standards, then adaptability is improved, but control overhead increases
Solution Approach 1:
The patent pre-configures multiple dataflow patterns and operational modes within the processing elements during manufacturing or initialization. When a specific wireless standard needs to be executed, the system simply activates the corresponding pre-configured pattern rather than dynamically reconfiguring the entire architecture, significantly reducing control overhead while maintaining adaptability to different standards.
Solution Approach 2:
The system achieves reconfiguration by changing operational parameters (such as dataflow direction, functional unit activation, and interconnect routing) rather than physically reconfiguring the hardware structure. This parameter-based approach allows rapid adaptation to different wireless standards with minimal control overhead, as it involves simple register writes rather than complex reconfiguration sequences.
Data Source
AI summary
A domain adaptive systolic-array-processor is presented with 256 programmable cores in a 12 nm CMOS for wireless communication workloads. The domain adaptive processor uses a globally homogeneous but locally heterogeneous architecture, decode-less reconfiguration instructions for data streaming, single-cycle data communication between functional units (FUs), and lightweight nested-loop control. This disclosure shows how configuration flexibility and fast program loading allows a wide range of communication workloads to be mapped and swapped in sub-μs, supporting continually evolving communication standards such as 5G. The domain adaptive processor achieves 507 GMACs/J and a peak performance of 264 GMACs.