Domain Merger Cell Layout for Adjacent Voltage Domain Isolation

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Solution Overview

Problem

Existing chip layouts with multiple voltage domains are inefficient due to empty areas between domains, which consume chip area without providing functionality.

Innovation Solution

The implementation of domain merger cells, which merge two voltage domains by using a merger cell with separate supply rails and n-taps, eliminating the need for empty areas between domains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage domains are separated by empty areas to prevent interference, then reliability is improved, but chip area increases

Engineering Contradiction:

Improvevoltage domain isolationVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges two adjacent voltage domains by placing a merger cell at their boundary, allowing the domains to share common infrastructure (substrate, n-wells, supply rails) while maintaining electrical isolation through proper potential management, thereby eliminating the need for empty separation areas

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The merger cell acts as an intermediary structure between two voltage domains with different potentials. It includes n-wells and n-taps that are properly potential-managed to prevent latch-up while enabling adjacent domains to operate at different voltages without requiring physical empty spaces for isolation

Inventive Principle:

Principle #24Intermediary (Mediator)

2Area of stationary object

If merger cells are used to eliminate empty areas, then chip area is reduced, but device complexity increases

Engineering Contradiction:

Improvechip areaVSAvoidmerger cell structure

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The merger cell is designed as a universal building block that can be placed at any boundary between adjacent voltage domains. It performs multiple functions: maintaining latch-up immunity, enabling different supply voltages, and eliminating empty areas, making it a multi-functional component that simplifies overall chip design despite its internal complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250072110A1Domain merger cell to abut power domains for chip area reduction

Publication Date: 2025.02.27 QUALCOMM INC

AI summary

A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.