Domain switching devices and methods of manufacturing the same
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Solution Overview
Problem
Existing silicon-based transistors face limitations in reducing operating voltage and scaling down due to the Boltzmann distribution of electrons, leading to increased power density and heat-related device failures.
Innovation Solution
A domain switching device with a channel region, source, and drain, featuring an anti-ferroelectric layer between the channel and gate electrode, a conductive layer in contact with the anti-ferroelectric layer, and a barrier layer, which allows for low operating voltage and enhanced control efficiency by inducing anti-ferroelectricity through crystallization and tensile stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If silicon-based transistors are scaled down to reduce device size, then device distribution density is increased, but power density increases and heat causes device failure
Solution Approach 1:
The patent changes the material parameter of the gate insulator from conventional silicon dioxide to hafnium oxide (HfO2), which has a higher dielectric constant. This material parameter change enables lower operating voltages and reduced power consumption while maintaining device functionality at scaled dimensions
Solution Approach 2:
The patent employs a composite gate structure combining hafnium oxide gate insulator with metal gate electrode (such as tungsten or titanium nitride). This composite material approach optimizes both electrical performance and thermal management, enabling scaled devices to operate with lower power density
2Loss of energy
If operating voltage is reduced below 0.8 V to lower power consumption, then power density decreases, but it becomes difficult to maintain proper transistor operation
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulator by using hafnium oxide (k≈25) instead of silicon dioxide (k≈3.9). This parameter change increases the gate capacitance, enabling effective transistor control at lower operating voltages while maintaining reliable switching operation
Solution Approach 2:
The patent utilizes the ferroelectric phase transition properties of crystalline hafnium oxide. By controlling the crystal phase (tetragonal or orthorhombic), the material exhibits negative capacitance effect that amplifies the gate voltage, enabling ultra-low voltage operation with maintained reliability
3Productivity
If device distribution density is increased to improve integration, then more devices fit on chip, but heat generated causes device failure
Solution Approach 1:
The patent changes the operating voltage parameter to lower values (below 0.8V, potentially 0.5V or lower) enabled by the high-k gate insulator. This parameter change reduces the power consumption (P=CV²f) of each device, thereby reducing heat generation and allowing higher device distribution density without thermal failure
Solution Approach 2:
The patent converts the typically harmful effect of scaling (increased power density and heat) into a benefit by using the high-k material's ability to operate at lower voltages. The scaling that would normally cause heat problems instead enables lower power operation when combined with hafnium oxide, turning the scaling challenge into a performance advantage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables improved subthreshold swing and control efficiency, facilitating the scaling down of devices while reducing power consumption and heat-related failures.
Implementation Method 1
At least a portion of the anti-ferroelectric layer adjacent to the conductive layer may be crystallized
Implementation Method 2
A thermal expansion coefficient of the conductive layer may be smaller than a thermal expansion coefficient of the anti-ferroelectric layer
Data Source
AI summary
A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.