Domain Wall Magnetic Memory Cell With BJT Selector
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Solution Overview
Problem
Conventional magnetic memory cells require high currents for programming, leading to high power consumption and suffer from low sensing margin, which results in reliability issues.
Innovation Solution
The development of a magnetic resistive memory cell with a domain wall magnetic element, incorporating a free layer with pinning layers and a reference stack, and a selector unit comprising bipolar junction transistors (BJTs) to reduce power consumption and enhance sensing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional magnetic memory cells use high currents for programming, then the magnetic orientation can be flipped, but power consumption increases
Solution Approach 1:
The memory cell is segmented into two separate MTJ elements: a storage MTJ for data retention and a sensing MTJ for read operations. This segmentation allows independent optimization of each element, enabling the storage MTJ to use lower programming currents while maintaining reliable magnetic orientation switching through domain wall manipulation mechanisms.
Solution Approach 2:
The patent employs parameter changes in the magnetic layer structure, including using elongated free layers with specific dimensions (e.g., 50-200 nm length), controlling magnetization directions, and adjusting coercivity parameters. These parameter optimizations enable reliable switching at reduced current levels by enhancing domain wall nucleation and propagation efficiency.
2Area of stationary object
If conventional magnetic memory cells are designed for compactness, then density increases, but sensing margin decreases
Solution Approach 1:
The patent transitions from planar MTJ structures to vertically stacked configurations with elongated free layers extending in the lateral direction. This dimensional change allows the sensing MTJ to achieve larger effective sensing area and improved sensing margin while maintaining a compact footprint by utilizing the vertical stacking architecture.
Solution Approach 2:
The sensing MTJ is designed with local quality optimizations, including elongated free layers with specific aspect ratios and positioned asymmetrically relative to the pinned layer. This local structural differentiation enhances the sensing signal strength in the critical read region while keeping the overall cell area compact through shared infrastructure with the storage MTJ.
3Ease of manufacture
If conventional magnetic memory cells use simple structures, then manufacturing is easier, but sensing margin and reliability are low
Solution Approach 1:
The patent implements a nested structure where the sensing MTJ is integrated within the same cell footprint as the storage MTJ, with shared pinned layers and interconnect structures. This nesting approach enables complex functionality (dual MTJ operation with improved sensing) to be manufactured using extended versions of standard spin-coating and sputtering processes, maintaining ease of manufacture while achieving superior reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-density memory cells with lower power consumption and improved sensing margin, enhancing the reliability of magnetic memory devices.
Implementation Method 1
spin transfer torque magnetoresistive random access memory (STT-MRAM) devices
Implementation Method 2
The electrical resistance of the MTJ element changes corresponding to the magnetic orientation of the free layer relating to the fixed magnetic layer
Implementation Method 3
a first pinning layer which is coupled to the first BJT terminal of the first BJT, a second pinning layer which is coupled to the first BJT terminal of the second BJT
Data Source
AI summary
Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit. The storage unit includes a first pinning layer which is coupled to the first BJT terminal of the first BJT, a second pinning layer which is coupled to the first BJT terminal of the second BJT, a free layer which includes an elongated member with first and second major surfaces and first and second end regions separated by a free region. The first pinning layer is coupled to the second major surface of the free layer in the first end region and the second pinning layer is coupled to the second major surface of the free layer in the second end region. A reference stack is disposed on the first major surface of the free layer in the free region. The reference stack serves as a read bitline terminal.