Dopant Diffusion Blocking Superlattices for Semiconductor Contact Resistance
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Solution Overview
Problem
Current semiconductor devices face limitations in achieving enhanced performance due to high source and drain contact resistance, which affects mobility and efficiency.
Innovation Solution
The implementation of a semiconductor device with a dopant diffusion blocking superlattice in the source and drain regions, comprising stacked groups of semiconductor and non-semiconductor monolayers, reduces contact resistance by modifying the energy band structure and trapping dopants, thereby enhancing charge carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source and drain regions are used in semiconductor devices, then the device structure is simple, but high contact resistance occurs at the metal-semiconductor interface
Solution Approach 1:
The source and drain regions are segmented into multiple sub-regions with different dopant concentrations by inserting dopant diffusion blocking superlattices at specific depths. This creates a graded dopant profile that reduces Schottky barrier height at the metal-semiconductor interface while maintaining structural organization through repeated superlattice units.
Solution Approach 2:
Different portions of the source/drain regions are doped to different concentrations based on their specific functional requirements. The upper portions near the metal contact have higher dopant concentrations to reduce contact resistance, while lower portions have lower concentrations to maintain mobility and prevent diffusion into the channel.
2Reliability
If dopant concentration is increased in source/drain regions to reduce contact resistance, then contact resistance decreases, but dopant diffusion into the channel region increases
Solution Approach 1:
Dopant diffusion blocking superlattices are inserted as intermediary layers between regions of different dopant concentrations. These superlattices act as diffusion barriers that prevent dopant atoms from migrating into the channel region while allowing the higher dopant concentrations needed for low contact resistance to be maintained in the source/drain regions.
Solution Approach 2:
The dopant concentration parameter is varied spatially within the source/drain regions by controlling the depth and positioning of dopant diffusion blocking superlattices. This creates a graded dopant profile where concentration increases toward the metal contact interface, optimizing both contact resistance and dopant distribution stability.
3Speed
If strained material layers are used to enhance carrier mobility, then device speed and performance improve, but manufacturing complexity increases
Solution Approach 1:
The device structure incorporates composite material layers including silicon-germanium strained layers and dopant diffusion blocking superlattices. These composite structures provide both the strain-induced mobility enhancement and the dopant diffusion blocking functionality, achieving performance improvement through integrated material design rather than separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration leads to reduced Schottky barrier height and contact resistance, improving charge carrier mobility and device performance, while also providing a barrier to dopant diffusion and scattering effects.
Implementation Method 1
reduces contact resistance by modifying the energy band structure
Implementation Method 2
trapping dopants, thereby enhancing charge carrier mobility
Implementation Method 3
U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Implementation Method 4
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Data Source
AI summary
A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.