Doped Cap Dielectric Openings for 3D NAND Pillar Alignment
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Solution Overview
Problem
As 3D NAND memory devices increase in density, the aspect ratios of pillars grow, leading to increased possibilities for pillar misalignment and reduced connectivity, along with higher parasitic capacitance due to decreased dimensions and spacing of conductive features, causing power demands and delays.
Innovation Solution
A doped cap dielectric material with heterogeneous dopant distribution is used, allowing for selective removal to form conductive structure openings with dimensions matching the critical dimensions of underlying pillars, reducing parasitic capacitance and misalignment between conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density increases in 3D NAND memory devices, then storage capacity improves, but pillar aspect ratios increase leading to misalignment and connectivity issues
Solution Approach 1:
The cap dielectric material is segmented into multiple layers with different dopant concentrations (first cap dielectric layer with first dopant concentration, second cap dielectric layer with second dopant concentration). This segmentation allows different etch rates for different layers, enabling precise control over opening dimensions and alignment with underlying pillars while maintaining high memory density.
Solution Approach 2:
Different regions of the cap dielectric structure are given different dopant concentrations to create local variations in etchability. The first cap dielectric layer has a different dopant concentration than the second cap dielectric layer, allowing selective removal of specific portions to achieve precise alignment with pillars without affecting overall memory density.
2Quantity of substance
If dimensions and spacing of conductive features decrease, then memory density increases, but parasitic capacitance between adjacent conductive features increases
Solution Approach 1:
The cap dielectric is segmented into multiple layers with different dopant concentrations, enabling precise control of opening dimensions. This allows conductive features to be formed with minimized spacing and dimensions while maintaining adequate separation to reduce parasitic capacitance between adjacent features.
Solution Approach 2:
The dopant concentration parameter is varied across different cap dielectric layers to control etch rates and final opening dimensions. By adjusting dopant concentrations, the spacing and dimensions of conductive features can be optimized to reduce parasitic capacitance while increasing memory density.
3Quantity of substance
If dimensions and spacing of conductive features decrease, then memory density increases, but manufacturing precision required to avoid shorts increases
Solution Approach 1:
The cap dielectric is divided into multiple layers with different dopant concentrations, allowing multi-stage etching processes that provide better control over opening dimensions. This segmentation enables precise formation of conductive features with reduced dimensions while maintaining adequate spacing to avoid shorts.
Solution Approach 2:
The cap dielectric layers are prepared in advance with specific dopant concentration profiles before the etching process. This preliminary preparation of the cap dielectric structure enables controlled removal of material to achieve precise conductive feature dimensions and spacing, reducing the risk of shorts while increasing memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and misalignment, enabling precise formation of conductive structures with reduced dimensions, thereby improving connectivity and reducing the likelihood of shorts in 3D NAND memory devices.
Implementation Method 1
Portions of the doped cap dielectric material are removed by different removal processes to form conductive structure openings
Data Source
AI summary
A microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. The doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. Conductive contact structures are in the doped dielectric material. Additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.